Chapter 2 Function Block
D-F/F (CB) with SB, 2 to 1 Selector
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
CB
OUT
MIN.
(LH) 0.385
(LL) 0.377
(LH) 0.529
(LL) 0.511
(LH) 0.330
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
0.636
0.615
0.895
0.853
0.618
0.383
1.206
1.160
1.790
1.618
1.169
0.656
1.820
1.810
1.950
0.080
0.080
0.000
0.720
0.460
2.125
1.502
1.205
1.162
1.042
1.820
1.820
1.940
0.080
0.080
0.000
0.720
0.460
1.530
1.364
1.041
1.081
0.921
1.790
1.790
1.920
0.080
0.080
0.000
0.680
0.430
1.414
1.257
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.018
D0
D1
CB
SB
A
1.0
1.0
1.0
2.2
1.0
Q
35
34
F666S
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
CB
→
QB
Low Power
F666S
11
F666SQ
10
F666SB
10
x1
x2
x4
SB
SB
→
→
Q
QB
(LL)
D0
D1
A
D0
D1
A
SB
SB
CB
SB
0.189
0.720
0.720
0.750
0.290
0.290
0.300
0.410
0.410
0.735
0.576
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
D0
D1
CB
SB
A
Q
QB
H04
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
0
1
1
D0 H01
D1 H02
N01
Q
0
X
X
X
X
X
Hold
1
Min Pulse
(LH) 0.384
(LL) 0.376
(LH) 0.314
0.635
0.614
0.553
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
D0
D1
CB
SB
A
1.0
1.0
1.0
2.2
1.0
Q
35
0
1
F666SQ
CB
→
Q
Q
CB H03
1
0
A
H05
N02 QB
SB
→
X
X
Hold
0
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
SB
SB
CB
SB
0.720
0.720
0.750
0.290
0.290
0.300
0.410
0.410
0.589
0.527
X
1
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
D0
D1
CB
SB
A
Q
H04
Min Pulse
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
0
1
(LH) 0.335
0.545
0.572
0.496
0.011
0.011
0.010
0.016
0.014
0.014
0.023
0.020
0.019
D0
D1
CB
SB
A
1.0
1.0
1.0
2.2
1.0
QB
32
F666SB
CB
→
QB
QB
D0 H01
D1 H02
N01
Q
(LL)
(LL)
D0
D1
A
D0
D1
A
SB
SB
CB
SB
0.343
0.281
0.730
0.730
0.750
0.290
0.290
0.300
0.420
0.390
0.559
0.514
X
X
X
X
X
Hold
0
SB
→
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
CB H03
1
1
A
H05
X
X
Hold
1
X
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
Min Pulse
SB
D0
D1
CB
SB
A
QB
H04
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
1
0
D0 H01
D1 H02
X
X
X
X
X
Hold
1
CB H03
1
0
A
H05
N01 QB
X
X
Hold
0
X
X:Irrelevant
Block Library A13872EJ5V0BL
2 - 304
Block Library A13872EJ5V0BL
2 - 305
ETC [ ETC ]
