Chapter 2 Function Block
D-F/F with RB, 2 to 1 Selector
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.012
0.010
0.012
0.010
0.010
0.012
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
(HH) 0.423
(HL) 0.422
(HH) 0.521
(HL) 0.556
0.199
(LH) 0.305
0.673
0.685
0.856
0.902
0.311
0.567
1.278
1.274
1.620
1.723
0.535
1.028
1.560
1.570
1.720
0.000
0.000
0.000
0.000
1.010
2.104
1.337
1.282
1.276
0.537
1.570
1.570
1.720
0.000
0.000
0.000
0.000
1.010
1.664
0.837
1.051
1.010
1.443
1.550
1.550
1.700
0.000
0.000
0.000
0.000
0.960
1.426
1.743
0.016
0.013
0.016
0.013
0.013
0.016
0.023
0.017
0.022
0.017
0.017
0.022
D0
D1
C
RB
A
1.0
1.0
1.0
2.2
1.0
Q
31
31
F615S
C
C
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
→
QB
Low Power
F615S
11
F615SQ
10
F615SB
10
x1
x2
x4
(LL)
RB
RB
→
→
Q
QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
RB
RB
C
0.700
0.700
0.700
0.270
0.270
0.250
0.190
0.670
0.747
0.547
Logic Diagram for "Normal"
Truth Table for "Normal"
D0
D1
C
RB
A
Q
QB
D0 H01
D1 H02
N01
Q
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
0
1
1
0
C
A
H03
H05
X
X
X
X
X
Hold
1
Min Pulse
RB
N02 QB
(HH) 0.423
(HL) 0.422
0.674
0.684
0.312
0.012
0.010
0.010
0.016
0.013
0.013
0.023
0.017
0.017
D0
D1
C
RB
A
1.0
1.0
1.0
2.3
1.0
Q
31
0
1
F615SQ
C
→
Q
Q
1
0
H04
RB
(LL)
D0
D1
A
D0
D1
A
RB
RB
C
0.199
0.700
0.700
0.700
0.260
0.270
0.250
0.190
0.670
0.614
0.384
RB
→
X
X
Hold
1
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
X
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
D0
D1
C
RB
A
Q
D0 H01
D1 H02
N01
Q
Min Pulse
RB
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
0
1
(HH) 0.351
(HL) 0.356
(LH) 0.327
0.564
0.567
0.748
0.012
0.011
0.012
0.016
0.014
0.016
0.023
0.020
0.023
D0
D1
C
RB
A
1.0
1.0
1.0
2.3
1.0
QB
31
F615SB
C
→
QB
QB
C
A
H03
H05
X
X
X
X
X
Hold
0
RB
→
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
RB
RB
C
0.710
0.710
0.700
0.270
0.270
0.250
0.170
0.630
0.548
0.626
1
1
H04
RB
X
X
Hold
0
X
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
Min Pulse
RB
D0
D1
C
RB
A
QB
D0 H01
D1 H02
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
1
0
C
A
H03
H05
X
X
X
X
X
Hold
1
N01 QB
1
0
H04
RB
X
X
Hold
1
X
X:Irrelevant
Block Library A13872EJ5V0BL
2 - 294
Block Library A13872EJ5V0BL
2 - 295
ETC [ ETC ]
