Chapter 2 Function Block
8-Bit Odd Parity Generator
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
High speed
(HH) 0.568
(HL) 0.560
(LH) 0.626
0.974
0.935
1.110
0.992
1.035
0.914
1.077
1.035
0.935
0.930
1.076
0.958
1.002
0.908
1.041
0.998
0.945
0.934
1.080
0.983
1.008
0.912
1.048
1.023
0.919
0.942
1.058
0.979
0.985
0.920
1.023
1.021
2.017
1.849
2.373
1.838
2.203
1.823
2.246
2.017
1.881
1.810
2.251
1.748
2.071
1.783
2.111
1.926
1.894
1.817
2.252
1.792
2.078
1.790
2.120
1.973
1.773
1.797
2.141
1.747
1.968
1.770
1.999
1.926
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.015
0.012
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
0.017
A
B
C
D
E
F
1.7
2.0
1.7
2.0
1.7
2.0
1.7
2.0
YO
33
F581
A
B
C
D
E
F
→
→
→
→
→
→
→
→
YO
YO
YO
YO
YO
YO
YO
YO
Drivability
Name cells
Name cells
Low Power
x1
(LL)
0.606
F581
19
(HH) 0.601
(HL) 0.544
(LH) 0.623
x2
x4
G
H
(LL)
0.599
(HH) 0.554
(HL) 0.561
(LH) 0.616
Logic Diagram
(LL)
0.593
A
B
C
D
E
F
H01
(HH) 0.588
(HL) 0.544
(LH) 0.611
H02
H03
H04
H05
H06
H07
H08
(LL)
0.585
(HH) 0.561
(HL) 0.565
(LH) 0.618
(LL)
0.606
G
H
(HH) 0.592
(HL) 0.549
(LH) 0.616
N01 YO
(LL)
0.599
(HH) 0.556
(HL) 0.577
(LH) 0.618
G
H
(LL)
0.614
(HH) 0.592
(HL) 0.561
(LH) 0.612
Truth Table
A
(LL)
0.607
B
C
D
E
F
G
H
YO
Σ of 1’s at A through H is Odd
Σ of 1’s at A through H is Even
1
0
Block Library A13872EJ5V0BL
2 - 218
Block Library A13872EJ5V0BL
2 - 219
ETC [ ETC ]
