Chapter 2 Function Block
Chapter 2 Function Block
Switching speed
4-Bit Full Adder
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Block type
IN
A1
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.013
0.015
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.013
0.015
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.012
0.014
0.011
0.010
0.011
0.010
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
High speed
Name cells
(HH) 0.424
(HL) 0.519
(LH) 0.810
0.717
0.853
1.352
0.874
1.207
2.030
1.241
0.806
1.638
2.418
1.538
1.144
2.110
2.625
1.741
1.481
2.207
1.531
0.783
0.827
1.273
0.917
1.181
2.004
1.260
0.831
1.613
2.392
1.553
1.157
2.084
2.600
1.757
1.495
2.182
1.546
0.713
0.842
1.318
0.871
1.222
1.816
1.134
0.818
1.625
2.039
1.340
1.131
1.667
1.136
0.782
0.817
1.241
0.915
1.197
1.790
1.454
1.667
2.673
1.585
2.394
3.804
2.343
1.564
3.315
4.776
3.068
2.255
4.360
5.315
3.601
3.002
4.624
3.140
1.652
1.637
2.421
1.765
2.366
3.774
2.333
1.575
3.286
4.746
3.070
2.237
4.331
5.286
3.598
2.996
4.595
3.140
1.450
1.647
2.633
1.581
2.420
3.478
2.176
1.580
3.294
4.036
2.698
2.242
3.421
2.266
1.646
1.619
2.385
1.759
2.392
3.449
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.019
0.021
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.019
0.021
0.015
0.012
0.015
0.012
0.015
0.013
0.015
0.012
0.015
0.013
0.015
0.012
0.018
0.020
0.015
0.012
0.015
0.012
0.015
0.013
0.021
0.017
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.018
0.022
0.017
0.029
0.031
0.021
0.017
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.019
0.022
0.017
0.021
0.018
0.022
0.017
0.029
0.031
0.021
0.017
0.022
0.017
0.021
0.018
0.022
0.017
0.021
0.018
0.022
0.017
0.027
0.029
0.022
0.017
0.022
0.017
0.021
0.018
A1
B1
A2
B2
A3
B3
A4
B4
CIN
1.7
2.1
1.7
2.1
1.7
2.1
1.7
2.0
2.1
S1
S2
31
30
29
28
18
F523
→
→
→
→
S1
S2
S3
S4
Drivability
Name cells
S3
Low Power
x1
(LL)
0.537
S4
F523
32
(HH) 0.723
(HL) 1.292
(LH) 0.730
COUT
A1
A1
A1
x2
x4
(LL)
0.474
(HH) 0.974
(HL) 1.476
(LH) 0.876
Logic Diagram
B4 H08
A4 H07
B3 H06
A3 H05
B2 H04
A2 H03
B1 H02
A1 H01
CIN H09
N05 COUT
N04 S4
N03 S3
N02 S2
N01 S1
(LL)
0.665
(HH) 1.239
(HL) 1.579
(LH) 0.976
(LL)
(HH) 1.302
(LL) 0.865
0.851
A1
B1
→
→
COUT
S1
(HH) 0.457
(HL) 0.498
(LH) 0.774
(LL)
0.529
(HH) 0.701
(HL) 1.270
(LH) 0.745
B1
B1
B1
→
→
→
S2
S3
S4
(LL)
0.492
(HH) 0.953
(HL) 1.455
(LH) 0.885
Truth Table
(LL)
0.678
(HH) 1.217
(HL) 1.558
(LH) 0.985
An
Bn
CIN
Sn
COUT
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
(LL)
(HH) 1.281
(LL) 0.874
0.864
B1
A2
→
→
COUT
S2
(HH) 0.422
(HL) 0.511
(LH) 0.784
(LL)
0.536
(HH) 0.733
(HL) 1.131
(LH) 0.665
A2
A2
→
→
S3
S4
(LL)
0.481
(Condition of one stage, n=1,2,3 4)
(HH) 0.964
(HL) 1.243
(LH) 0.768
(LL)
(HH) 0.996
(LL) 0.655
0.654
A2
B2
→
→
COUT
S2
(HH) 0.457
(HL) 0.490
(LH) 0.751
0.530
(HH) 0.712
(HL) 1.110
(LL)
B2
→
S3
Block Library A13872EJ5V0BL
2 - 188
Block Library A13872EJ5V0BL
2 - 189
ETC [ ETC ]
