Chapter 2 Function Block
Chapter 2 Function Block
Switching speed
3-Input OR
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
-
Block type
Drivability
Low Power
x1
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
IN
OUT
MIN.
(HH) 0.130
(LL) 0.267
(HH) 0.145
(LL) 0.270
(HH) 0.153
(LL) 0.272
(HH) 0.145
(LL) 0.307
(HH) 0.159
(LL) 0.312
(HH) 0.170
(LL) 0.317
(HH) 0.191
(LL) 0.412
(HH) 0.203
(LL) 0.416
(HH) 0.215
(LL) 0.420
TYP. MAX.
MIN.
0.022
0.021
0.022
0.021
0.022
0.021
0.011
0.011
0.011
0.011
0.011
0.011
0.006
0.006
0.006
0.006
0.006
0.006
TYP. MAX. Symbol Fanin Symbol Fanout
Name cells
Name cells
Name cells
Name cells
Name cells
0.212
0.404
0.232
0.433
0.244
0.485
0.223
0.468
0.241
0.500
0.258
0.557
0.278
0.642
0.296
0.679
0.315
0.736
0.347
0.645
0.384
0.803
0.404
0.985
0.355
0.759
0.397
0.927
0.419
1.113
0.449
1.101
0.493
1.274
0.525
1.457
0.030
0.027
0.030
0.027
0.030
0.027
0.015
0.014
0.015
0.014
0.015
0.014
0.008
0.008
0.008
0.008
0.008
0.008
0.042
0.038
0.042
0.038
0.043
0.037
0.021
0.020
0.021
0.020
0.022
0.020
0.011
0.011
0.011
0.011
0.011
0.011
A
B
C
1.0
1.0
1.0
Y
Y
Y
16
34
68
L213
F213
F233
A
B
C
A
B
C
A
B
C
→
→
→
→
→
→
→
→
→
Y
Y
Y
Y
Y
Y
Y
Y
Y
L213
2
F213
F233
3
4
x2
x4
A
B
C
1.0
1.0
1.0
x8
Block type
Normal
with 1 inverter with 2 inverter with 3 inverter with 4 inverter
-
cells
Drivability
Name
Name cells
Name cells
Name cells
Name cells
Low Power
x1
x2
x4
x8
A
B
C
1.0
1.0
1.0
Logic Diagram for "Normal"
Logic Diagram for "with 1 inverter"
Logic Diagram for "with 2 inverter"
A
B
C
H01
H02
H03
N01
Y
Logic Diagram for "with 3 inverter"
Logic Diagram for "with 4 inverter"
Block Library A13872EJ5V0BL
2 - 36
Block Library A13872EJ5V0BL
2 - 37
ETC [ ETC ]
