Chapter 1 Interface Block
Low-noise Schmitt I/O Buffer
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
TTL 5.0 V
Function
Block type
BFIVW
Path
→
t 1
T
Block type
with 50 KΩ P/U
IN
OUT
MIN.
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.906
0.903
0.697
0.638
0.907
0.940
1.184
2.208
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
0.951
0.874
0.948
0.817
0.943
0.868
1.184
2.208
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
0.059
0.103
Drivability
1mA
no resistor
with 50 KΩ P/D
with 5 KΩ P/U
I/O cells int. Cells
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.649
1.561
0.916
0.928
1.682
1.673
1.976
3.267
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
1.724
1.428
1.269
1.158
1.755
1.494
1.976
3.267
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.217
3.193
1.493
1.536
4.261
3.375
4.048
5.483
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
4.530
2.630
2.217
1.799
4.570
2.680
4.048
5.483
0.044
0.077
0.086
0.150
A
→
Y0
EN
→
Y0
2mA
3mA
0.044
0.077
0.059
0.104
0.086
0.151
BFIVW
BFDVW
BFUVW
BFWVW
1
13
0.008
0.012
0.011
0.015
0.017
0.022
Y0
A
→
→
→
Y1
Y0
Y0
6mA
BFIDW
BFI4W
BFDDW
BFD4W
BFUDW
BFU4W
BFWDW
BFW4W
1
1
13
13
0.044
0.077
0.059
0.103
0.086
0.150
9mA
BFDVW
BFUVW
BFWVW
BFIDW
12mA
18mA
24mA
BFI2W
BFI6W
BFIGW
BFD2W
BFD6W
BFDGW
BFU2W
BFU6W
BFUGW
BFW2W
BFW6W
1
1
1
13
13
13
EN
0.044
0.077
0.059
0.104
0.086
0.151
BFWGW
Input
0.008
0.012
0.011
0.015
0.017
0.022
Y0
A
→
→
→
Y1
Y0
Y0
Output
Logic Diagram
Block type
Symbol Fan-in Symbol Fan-out
0.044
0.077
0.059
0.103
0.086
0.150
BFIVW to BFWVW
A
6.2
4.0
Y1
Y1
Y1
Y1
Y1
Y1
37
37
37
37
37
37
EN
EN
Y1 N02
0.044
0.077
0.059
0.104
0.086
0.151
BFIDW to BFWDW
BFI4W to BFW4W
BFI2W to BFW2W
BFI6W to BFW6W
BFIGW to BFWGW
A
6.1
4.0
0.008
0.012
0.011
0.015
0.017
0.022
EN
Y0
A
→
→
→
Y1
Y0
Y0
0.044
0.077
0.059
0.103
0.086
0.150
A
H02
N01 Y0
A
6.2
4.0
EN
EN
0.044
0.077
0.059
0.104
0.086
0.151
EN H03
A
6.2
4.0
EN
0.008
0.012
0.011
0.015
0.017
0.022
Y0
A
→
→
→
Y1
Y0
Y0
0.031
0.039
0.042
0.053
0.066
0.075
A
6.2
4.0
Truth Table
EN
EN
A
EN
Y0
0.031
0.040
0.042
0.054
0.066
0.077
A
6.2
4.0
0
1
X
1
1
0
0
1
Z
EN
0.008
0.012
0.011
0.015
0.017
0.022
Y0
A
→
→
→
Y1
Y0
Y0
0.031
0.039
0.042
0.053
0.066
0.075
BFDDW
BFUDW
X:Irrelevant
EN
Z:High Impedance
0.031
0.040
0.042
0.054
0.066
0.077
Y0
Y1
0.008
0.012
0.011
0.015
0.017
0.022
Y0
A
→
→
→
Y1
Y0
Y0
0
1
0
1
0.031
0.039
0.042
0.053
0.066
0.075
EN
0.031
0.040
0.042
0.054
0.066
0.077
0.008
0.012
0.011
0.015
0.017
0.022
Y0
→
Y1
Block Library A13872EJ5V0BL
1 - 90
Block Library A13872EJ5V0BL
1 - 91
ETC [ ETC ]
