Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
CMOS 5.0 V
Function
Schmitt I/O Buffer
no resistor
Block type
BSIUW
Path
→
t 1
T
Block type
IN
OUT
MIN.
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.591
0.710
1.088
0.380
0.832
0.771
0.673
0.901
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
0.613
0.650
1.413
0.451
0.851
0.667
0.673
0.901
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
0.056
0.103
Drivability
1mA
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
(HH)
(LL)
(HZ)
(LZ)
(ZH)
(ZL)
(HH)
(LL)
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.045
1.257
1.523
0.577
1.425
1.385
0.949
1.332
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
1.080
1.081
1.971
0.675
1.454
1.152
0.949
1.332
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.529
2.776
2.712
0.996
3.216
2.985
1.621
2.207
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
2.673
2.183
3.618
1.128
3.330
2.242
1.621
2.207
0.042
0.076
0.080
0.149
A
→
Y0
EN
→
Y0
2mA
3mA
0.042
0.077
0.056
0.103
0.077
0.150
BSIUW
BSDUW
BSUUW
BSWUW
1
13
0.008
0.009
0.011
0.012
0.017
0.016
Y0
A
→
→
→
Y1
Y0
Y0
6mA
BSICW
BSI3W
BSDCW
BSD3W
BSUCW
BSU3W
BSWCW
BSW3W
1
1
13
13
0.042
0.076
0.056
0.103
0.080
0.149
9mA
BSDUW
BSUUW
BSWUW
BSICW
12mA
18mA
24mA
BSI1W
BSI5W
BSIFW
BSD1W
BSD5W
BSDFW
BSU1W
BSU5W
BSUFW
BSW1W
BSW5W
1
1
1
23
23
23
EN
0.042
0.077
0.056
0.103
0.077
0.150
BSWFW
Input
0.008
0.009
0.011
0.012
0.017
0.016
Y0
A
→
→
→
Y1
Y0
Y0
Output
Logic Diagram
Block type
Symbol Fan-in Symbol Fan-out
0.042
0.076
0.056
0.103
0.080
0.149
BSIUW to BSWUW
A
6.3
1.0
Y1
Y1
Y1
Y1
Y1
Y1
42
42
42
42
42
42
EN
EN
Y1 N02
0.042
0.077
0.056
0.103
0.077
0.150
BSICW to BSWCW
BSI3W to BSW3W
BSI1W to BSW1W
BSI5W to BSW5W
BSIFW to BSWFW
A
6.3
1.0
0.008
0.009
0.011
0.012
0.017
0.016
EN
Y0
A
→
→
→
Y1
Y0
Y0
0.042
0.076
0.056
0.103
0.080
0.149
A
H02
N01 Y0
A
6.3
1.0
EN
EN
0.042
0.077
0.056
0.103
0.077
0.150
EN H03
A
16.9
1.0
EN
0.008
0.009
0.011
0.012
0.017
0.016
Y0
A
→
→
→
Y1
Y0
Y0
0.029
0.038
0.039
0.051
0.057
0.073
A
16.9
1.0
Truth Table
EN
EN
A
EN
Y0
0.029
0.039
0.039
0.052
0.056
0.076
A
16.9
1.0
0
1
X
1
1
0
0
1
Z
EN
0.008
0.009
0.011
0.012
0.017
0.016
Y0
A
→
→
→
Y1
Y0
Y0
0.029
0.038
0.039
0.051
0.057
0.073
BSDCW
BSUCW
X:Irrelevant
EN
Z:High Impedance
0.029
0.039
0.039
0.052
0.056
0.076
Y0
Y1
0.008
0.009
0.011
0.012
0.017
0.016
Y0
A
→
→
→
Y1
Y0
Y0
0
1
0
1
0.029
0.038
0.039
0.051
0.057
0.073
EN
0.029
0.039
0.039
0.052
0.056
0.076
0.008
0.009
0.011
0.012
0.017
0.016
Y0
→
Y1
Block Library A13872EJ5V0BL
1 - 40
Block Library A13872EJ5V0BL
1 - 41
ETC [ ETC ]
