Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Function
Input Buffer
Block type
FI01
Path
→
t 1
T
Block type
IN
OUT
MIN.
0.160
0.103
0.160
0.103
0.160
0.103
0.160
0.103
0.673
0.901
0.673
0.901
0.673
0.901
0.673
0.901
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
Function
Normal
Schmitt
Clock
no resistor
FI01
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
0.236
0.168
0.236
0.168
0.236
0.168
0.236
0.168
0.949
1.332
0.949
1.332
0.949
1.332
0.949
1.332
0.452
0.328
0.452
0.328
0.452
0.328
0.452
0.328
1.621
2.207
1.621
2.207
1.621
2.207
1.621
2.207
0.007
0.010
0.007
0.010
0.007
0.010
0.007
0.010
0.008
0.009
0.008
0.009
0.008
0.009
0.008
0.009
0.010
0.012
0.010
0.012
0.010
0.012
0.010
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.011
0.012
0.014
0.017
0.014
0.017
0.014
0.017
0.014
0.017
0.017
0.016
0.017
0.016
0.017
0.016
0.017
0.016
A
A
A
A
A
A
A
A
→
→
→
→
→
→
→
→
Y
Y
Y
Y
Y
Y
Y
Y
FID1
FIU1
FIW1
1
1
3
6
FID1
FIS1W
FDS1W
FUS1W
FWS1W
FIU1
FIW1
Logic Diagram for "Normal"
Truth Table
FIS1W
FDS1W
FUS1W
FWS1W
A
Y
A
H01
N01
Y
1
0
1
0
Logic Diagram for "Schmitt"
Input
Output
Block type
FI01 to FIW1
Symbol Fan-In Symbol Fan-Out
A
A
-
-
Y
Y
52
42
A
H01
N01
Y
FIS1W to FWS1W
Logic Diagram for "Clock"
Block Library A13872EJ5V0BL
1 - 4
Block Library A13872EJ5V0BL
1 - 5
ETC [ ETC ]
