Chapter 2 Function Block
Chapter 2 Function Block
Switching speed
D-Latch with R
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
OUT
MIN.
(HH) 0.514
(LL) 0.428
TYP. MAX.
MIN.
0.011
0.010
0.010
0.011
0.011
0.010
0.011
0.010
0.010
0.011
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
0.840
0.724
0.641
0.494
0.930
0.758
0.530
0.732
0.578
0.598
0.259
0.398
1.600
1.379
1.181
0.947
1.783
1.389
0.961
1.364
1.039
1.207
0.439
0.789
1.110
0.000
0.620
0.190
2.112
1.428
1.274
1.218
1.444
1.233
0.915
0.870
0.930
0.000
0.340
0.470
1.769
1.188
1.255
0.942
1.214
1.030
1.019
1.409
1.490
0.000
1.580
0.000
1.545
1.620
1.186
0.949
0.963
1.369
0.440
0.794
1.000
0.000
0.520
0.300
1.697
1.005
0.015
0.013
0.013
0.015
0.015
0.013
0.015
0.013
0.013
0.015
0.015
0.013
0.021
0.017
0.019
0.021
0.021
0.017
0.021
0.019
0.018
0.021
0.022
0.019
D
G
R
1.0
1.0
1.0
Q
35
35
F602
D
D
G
G
R
R
→
→
→
→
→
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
(HL) 0.402
(LH) 0.292
(HH) 0.557
(HL) 0.473
(HH) 0.338
(HL) 0.445
(HL) 0.310
(LH) 0.354
(HH) 0.178
QB
Q
Low Power
L602
5
F602
6
F602NQ
6
F602NB
5
x1
x2
x4
QB
Q
Logic Diagram for "Normal"
Truth Table for "Normal"
QB
D
G
R
Q
QB
D
G
H01
H02
N01
Q
(LL)
0.242
0.650
0.210
0.470
0.340
0.690
0.627
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
G
R
1
0
1
1
0
X
0
0
0
1
1
0
0
1
X
X
Latch
N02 QB
0
1
Min Pulse
X:Irrelevant
(HH) 0.414
(LL) 0.369
0.672
0.633
0.752
0.672
0.507
0.425
0.021
0.020
0.021
0.020
0.020
0.021
0.029
0.025
0.029
0.025
0.026
0.029
0.042
0.034
0.042
0.034
0.036
0.042
D
G
R
1.0
1.0
1.0
Q
17
29
35
L602
D
G
R
→
→
→
Q
Q
Q
H03
R
(HH) 0.446
(HL) 0.411
(HL) 0.241
(LH) 0.251
0.570
Logic Diagram for "Q output"
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
G
R
Truth Table for "Q output"
0.250
0.390
0.420
0.574
D
G
R
Q
D
G
H01
H02
N01
Q
1
0
1
1
0
X
0
0
0
1
1
0
Min Pulse
0.472
(HH) 0.379
0.606
0.480
0.614
0.542
0.591
0.682
0.012
0.011
0.012
0.011
0.010
0.012
0.017
0.014
0.017
0.014
0.014
0.017
0.025
0.021
0.025
0.021
0.020
0.025
D
G
R
1.0
1.0
1.0
Q
F602NQ
D
G
R
→
→
→
Q
Q
Q
X
X
Latch
0
(LL)
0.281
(HH) 0.376
(HL) 0.330
(HL) 0.333
(LH) 0.398
0.750
X:Irrelevant
H03
R
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
G
R
0.240
0.680
0.190
0.514
Logic Diagram for "QB output"
Truth Table for "QB output"
Min Pulse
0.519
(HL) 0.402
(LH) 0.293
(HH) 0.338
(HL) 0.445
(HH) 0.178
0.643
0.495
0.531
0.733
0.259
0.401
0.010
0.011
0.011
0.010
0.011
0.010
0.013
0.015
0.015
0.013
0.015
0.013
0.019
0.021
0.021
0.019
0.022
0.019
D
G
R
1.0
1.0
1.0
QB
F602NB
D
G
R
→
→
→
QB
QB
QB
D
G
R
QB
D
G
H01
H02
1
0
1
1
0
X
0
0
0
1
0
1
X
X
Latch
1
(LL)
0.243
0.610
0.220
0.440
0.370
0.579
0.503
N01 QB
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
G
R
X:Irrelevant
H03
R
Min Pulse
Block Library A13872EJ5V0BL
2 - 238
Block Library A13872EJ5V0BL
2 - 239
ETC [ ETC ]
