Chapter 2 Function Block
8-Bit Even Parity Generator
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
0.011
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
High speed
(HH) 0.538
(HL) 0.533
(LH) 0.584
0.913
0.913
0.969
1.049
0.891
0.975
1.013
1.017
0.907
0.886
0.935
1.026
0.885
0.952
0.976
0.992
0.923
1.038
0.972
1.175
0.901
1.102
1.013
1.141
0.929
1.023
0.965
1.162
0.907
1.089
1.007
1.127
1.875
1.859
1.864
2.213
1.847
2.046
2.043
2.086
1.835
1.743
1.774
2.115
1.809
1.934
1.950
1.975
1.841
1.985
1.816
2.348
1.812
2.164
1.995
2.214
1.816
1.885
1.766
2.254
1.788
2.081
1.945
2.112
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.015
0.013
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.018
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
0.022
0.019
A
B
C
D
E
F
1.7
2.0
1.7
2.0
1.7
2.0
1.7
2.0
YE
33
F582
A
B
C
D
E
F
→
→
→
→
→
→
→
→
YE
YE
YE
YE
YE
YE
YE
YE
Drivability
Name cells
Name cells
Low Power
x1
(LL)
0.591
F582
19
(HH) 0.522
(HL) 0.566
(LH) 0.578
x2
x4
G
H
(LL)
0.588
(HH) 0.540
(HL) 0.524
(LH) 0.571
Logic Diagram
(LL)
0.586
A
B
C
D
E
F
H01
(HH) 0.523
(HL) 0.559
(LH) 0.563
H02
H03
H04
H05
H06
H07
H08
(LL)
0.582
(HH) 0.553
(HL) 0.622
(LH) 0.595
(LL)
0.681
G
H
(HH) 0.537
(HL) 0.655
(LH) 0.589
N01 YE
(LL)
0.678
(HH) 0.564
(HL) 0.622
(LH) 0.601
G
H
(LL)
0.683
(HH) 0.548
(HL) 0.659
(LH) 0.595
Truth Table
A
(LL)
0.678
B
C
D
E
F
G
H
YE
Σ of 1’s at A through H is Odd
Σ of 1’s at A through H is Even
0
1
Block Library A13872EJ5V0BL
2 - 220
Block Library A13872EJ5V0BL
2 - 221
ETC [ ETC ]
