Chapter 2 Function Block
Chapter 2 Function Block
Switching speed
Function
3-State Buffer
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Buffer type
Inverter type
Block type
IN
OUT
MIN.
(HH) 0.164
(LL) 0.176
(HZ) 0.346
(LZ) 0.221
(ZH) 0.291
(ZL) 0.254
(HH) 0.143
(LL) 0.164
(HZ) 0.337
(LZ) 0.231
(ZH) 0.271
(ZL) 0.244
(HH) 0.173
(LL) 0.194
(HZ) 0.402
(LZ) 0.260
(ZH) 0.289
(ZL) 0.265
(HH) 0.230
(LL) 0.262
(HZ) 0.532
(LZ) 0.329
(ZH) 0.328
(ZL) 0.320
(HH) 0.157
(LL) 0.185
(HZ) 0.284
(LZ) 0.293
(ZH) 0.215
(ZL) 0.315
(HH) 0.141
(LL) 0.167
(HZ) 0.286
(LZ) 0.301
(ZH) 0.196
(ZL) 0.297
(HH) 0.170
(LL) 0.200
(HZ) 0.336
(LZ) 0.335
(ZH) 0.209
(ZL) 0.322
(HH) 0.225
(LL) 0.271
(HZ) 0.444
(LZ) 0.414
(ZH) 0.242
(ZL) 0.388
TYP. MAX.
MIN.
0.022
0.020
TYP. MAX. Symbol Fanin Symbol Fanout
with EN
with ENB
with EN
with ENB
0.255
0.273
0.500
0.339
0.465
0.416
0.222
0.249
0.499
0.349
0.432
0.392
0.263
0.295
0.583
0.389
0.469
0.429
0.343
0.404
0.754
0.478
0.541
0.522
0.245
0.287
0.395
0.445
0.351
0.529
0.218
0.254
0.402
0.452
0.324
0.497
0.256
0.304
0.471
0.497
0.350
0.539
0.334
0.420
0.620
0.596
0.413
0.652
0.390
0.351
0.509
0.352
0.443
0.395
0.463
0.492
0.832
0.608
0.858
0.775
0.437
0.397
0.875
0.589
0.837
0.671
0.538
0.453
1.044
0.627
0.940
0.702
0.738
0.599
1.380
0.721
1.140
0.801
0.446
0.513
0.610
0.783
0.664
1.010
0.430
0.404
0.667
0.761
0.652
0.894
0.524
0.467
0.819
0.810
0.742
0.934
0.713
0.628
1.133
0.914
0.931
1.053
0.643
0.723
0.888
0.594
0.852
0.678
0.030
0.025
0.042
0.035
A
EN
Y
2.1
1.0
0.5
Y
Y
Y
Y
Y
Y
Y
Y
Y
17
L531
F531
F533
F53F
L532
F532
F534
F53G
F541
A
→
Y
Y
Drivability
Name cells
Name cells
Name cells
Name cells
EN
→
L531
F531
4
5
L532
F532
4
5
Low Power
x1
F541
6
F542
6
0.022
0.020
0.011
0.010
0.030
0.025
0.015
0.013
0.042
0.035
0.022
0.017
F533
F53F
7
F534
F53G
7
F543
F54F
8
F544
F54G
8
x2
x4
x8
A
EN
Y
2.1
1.0
0.5
34
A
→
→
Y
Y
11
11
12
12
EN
Logic Diagram for "Buffer with EN"
Logic Diagram for "Buffer with ENB"
0.011
0.010
0.006
0.005
0.015
0.013
0.008
0.007
0.022
0.018
0.011
0.009
A
EN
Y
2.1
1.0
1.0
67
A
→
→
Y
Y
EN
A
H01
N01
Y
A
H01
N01
Y
0.006
0.005
0.003
0.003
0.008
0.007
0.004
0.004
0.011
0.009
0.006
0.005
A
EN
Y
2.1
1.0
2.7
125
17
A
→
→
Y
Y
ENB H02
EN H02
EN
0.003
0.003
0.022
0.020
0.004
0.004
0.030
0.025
0.006
0.005
0.042
0.035
A
ENB
Y
2.1
1.0
0.5
A
→
→
Y
Y
Logic Diagram for "Inverter with EN"
Logic Diagram for "Inverter with ENB"
ENB
0.022
0.020
0.011
0.010
0.030
0.025
0.015
0.013
0.042
0.035
0.022
0.017
A
H01
N01
Y
A
H01
N01
Y
A
ENB
Y
2.1
1.0
0.5
34
A
→
→
Y
Y
ENB
ENB H02
EN H02
0.011
0.010
0.006
0.005
0.015
0.013
0.008
0.007
0.022
0.018
0.011
0.009
A
ENB
Y
2.1
1.0
1.0
67
A
→
→
Y
Y
ENB
0.006
0.005
0.003
0.003
0.008
0.007
0.004
0.004
0.011
0.009
0.006
0.005
Truth Table
With EN
A
ENB
Y
2.1
1.0
2.7
126
34
A
→
→
Y
Y
With ENB
A
ENB
A
EN
Y
Y*
ENB
Y
Y*
0.003
0.003
0.010
0.011
0.004
0.004
0.013
0.015
0.006
0.005
0.017
0.022
0
1
X
1
1
0
0
1
Z
1
0
Z
0
1
X
0
0
1
0
1
Z
1
0
Z
(HL) 0.252
(LH) 0.213
(HZ) 0.347
A
EN
Y
1.0
1.0
0.5
A
→
→
Y
Y
EN
X:Irrelevant
(LZ)
(ZH) 0.278
(ZL) 0.246
0.233
Z:High Impedance
*:Inverter type
0.011
0.010
0.015
0.013
0.022
0.018
Block Library A13872EJ5V0BL
2 - 198
Block Library A13872EJ5V0BL
2 - 199
ETC [ ETC ]
