Chapter 2 Function Block
Chapter 2 Function Block
Switching speed
1-Bit Full Adder
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.010
0.011
0.011
0.011
0.010
0.011
0.011
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
High speed
Name cells
(HH) 0.410
(HL) 0.481
(LH) 0.479
0.787
0.832
1.078
1.169
0.780
0.807
0.760
0.853
1.008
1.111
0.754
0.883
0.621
0.703
0.551
0.571
0.406
0.472
1.548
1.570
2.172
2.268
1.524
1.391
1.530
1.641
1.954
2.072
1.495
1.575
1.218
1.157
1.004
1.098
0.735
0.886
0.015
0.013
0.015
0.013
0.016
0.013
0.015
0.013
0.015
0.013
0.016
0.013
0.015
0.013
0.015
0.012
0.015
0.014
0.022
0.018
0.022
0.018
0.023
0.018
0.022
0.018
0.022
0.018
0.023
0.018
0.022
0.018
0.022
0.017
0.022
0.019
A
B
CIN
1.7
2.0
1.0
S
33
32
F521
A
→
S
Drivability
Name cells
COUT
Low Power
x1
(LL)
(HH) 0.357
(LL) 0.247
0.519
F521
9
A
B
→
→
COUT
S
x2
x4
(HH) 0.445
(HL) 0.484
(LH) 0.483
Logic Diagram
(LL)
(HH) 0.394
(LL) 0.216
0.515
B
→
→
COUT
S
A
B
H01
H02
N02 COUT
(HH) 0.382
(HL) 0.470
(LH) 0.339
CIN
(LL)
(HH) 0.271
(LL) 0.287
0.345
CIN
→
COUT
CIN H03
N01
S
Truth Table
A
B
CIN
S
COUT
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Block Library A13872EJ5V0BL
2 - 186
Block Library A13872EJ5V0BL
2 - 187
ETC [ ETC ]
