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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
(25Ω
Series) PI74FCT2273T
PI74FCT273T
(25Ω Series) P174FCT2273T
Ω
Octal D Flip-Flop
PI74FCT273T
with Master Reset
Product Features
PI74FCT273/2273T is pin compatible with bipolar FAST
Series at a higher speed and lower power consumption
25Ω series resistor on all outputs (FCT2XXX only)
TTL input and output levels
Low ground bounce outputs
Extremely low static power
Hysteresis on all inputs
Industrial operating temperature range: 40°C to +85°C
Packages available:
20-pin 173 mil wide plastic TSSOP (L)
20-pin 300 mil wide plastic DIP (P)
20-pin 150 mil wide plastic QSOP (Q)
20-pin 150 mil wide plastic TQSOP (R)
20-pin 300 mil wide plastic SOIC (S)
Product Description
Fast CMOS Octal D Flip-Flop
with Master Reset
Pericom Semiconductors PI74FCT series of logic circuits are pro-
duced in the Companys advanced 0.6/0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25-ohm series resistor on
all outputs to reduce noise because of reflections, thus eliminating
the need for an external terminating resistor.
The PI74FCT273T and PI74FCT2273T is an 8-bit wide octal
designed with eight edge-triggered D-type flip-flops with individual
D inputs and O outputs. The common buffered Clock (CP) and
Master Reset (MR) load and resets (clear) all flip-flops
simultaneously. The register is fully edge-triggered. The D input
state, one setup time before the LOW-to-HIGH clock transition, is
transferred to the corresponding flip-flop's O output. All outputs
will be forced LOW independently of Clock or Data inputs by a
LOW voltage level on the MR input.
Device models available upon request.
Logic Block Diagram
D
0
CP
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Product Pin Configuration
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
20
2
19
3
18
20-PIN
4
17
L20
5
16
P20
6
15
Q20
7
14
R20
8
13
S20
9
12
10
11
Product Pin Description
Pin Name
MR
CP
D
0
-D
7
O
0
-O
7
GND
V
CC
Description
Master Reset (Active LOW)
Clock Pulse Input
(Active Rising Edge)
Data Inputs
Data Outputs
Ground
Power
Truth Table
(1)
Inputs
Mode
MR
CP
Reset (Clear) L
X
Load "1"
H
↑
Load "0"
H
↑
D
N
X
h
l
Outputs
O
N
L
H
L
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
1. H = High Voltage Level
h = High Voltage Level one setup time
prior to the LOW-to-HIGH Clock
transition
L = Low Voltage Level
l = LOW Voltage Level one setup time
prior to the LOW-to-HIGH Clock
Transition
X = Dont Care
↑
= LOW-to-HIGH Clock Transition
PS2013A 03/09/96
1
ETC [ ETC ]
