Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
15
15
15
15
15
15
8
8
8
8
8
8
8
7
7
7
7
7
7
7
0
0
0
0
0
0
0
ADD, SUB, CMP,
ADDX, SUBX (Rm)
op
op
op
rm
rm
rm
rn
rn
rn
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
op
MULXU, DIVXU
ADD, ADDX, SUBX,
CMP (#XX:8)
op
op
rn
IMM
IMM
rn
rn
AND, OR, XOR (Rm)
AND, OR, XOR (#xx:8)
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
Notation:
op: Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes
34
ETC [ ETC ]
