CKSTPR1—Clock stop register 1
H'FA
System control
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer A module standby mode control
0
1
Timer A is set to module standby mode
Timer A module standby mode is cleared
Timer C module standby mode control
0
1
Timer C is set to module standby mode
Timer C module standby mode is cleared
Timer F module standby mode control
0
1
Timer F is set to module standby mode
Timer F module standby mode is cleared
Timer G interrupt enable
0
1
Timer G is set to module standby mode
Timer G module standby mode is cleared
A/D converter module standby mode control
0
1
A/D converter is set to module standby mode
A/D converter module standby mode is cleared
SCI3-2 module standby mode control
0
1
SCI3-2 is set to module standby mode
SCI3-2 module standby mode is cleared
SCI3-1 module standby mode control
0
1
SCI3-1 is set to module standby mode
SCI3-1 module standby mode is cleared
SCI1 module standby mode control
0
1
SCI1 is set to module standby mode
SCI1 module standby mode is cleared
471
ETC [ ETC ]
