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HD6433846XXXH 参数 Datasheet PDF下载

HD6433846XXXH图片预览
型号: HD6433846XXXH
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器\n [Microcontroller ]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 524 页 / 1465 K
品牌: ETC [ ETC ]
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4. TCF clear timing  
TCF can be cleared by a compare match with OCRF.  
5. Timer overflow flag (OVF) set timing  
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.  
6. Compare match flag set timing  
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.  
The compare match signal is generated in the last state during which the values match (when TCF  
is updated from the matching value to a new value). When TCF matches OCRF, the compare  
match signal is not generated until the next counter clock.  
7. Timer F operation modes  
Timer F operation modes are shown in table 9-10.  
Table 9-10 Timer F Operation Modes  
Operation  
Mode  
Module  
Reset  
Active  
Sleep  
Watch  
Subactive Subsleep Standby  
Standby  
TCF  
Reset  
Functions Functions Functions/ Functions/ Functions/ Halted  
Halted  
Halted*  
Held  
Halted*  
Halted*  
OCRF  
TCRF  
Reset  
Reset  
Reset  
Functions Held  
Functions Held  
Functions Held  
Functions Held  
Functions Held  
Functions Held  
Held  
Held  
Held  
Held  
Held  
Held  
Held  
TCSRF  
Held  
Note:  
*
When øw/4 is selected as the TCF internal clock in active mode or sleep mode, since  
the system clock and internal clock are mutually asynchronous, synchronization is  
maintained by a synchronization circuit. This results in a maximum count cycle error of  
1/ø (s). When the counter is operated in subactive mode, watch mode, or subsleep  
mode, øw/4 must be selected as the internal clock. The counter will not operate if any  
other internal clock is selected.  
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