Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose øOSC/128, øOSC/64, øOSC/32, or øOSC/16 as the operating clock in active
(medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in
active (high-speed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0
Description
øOSC/16
0
0
1
1
0
1
0
1
øOSC/32
øOSC/64
øOSC/128
(initial value)
2. System control register 2 (SYSCR2)
Bit
7
—
1
6
—
1
5
—
1
4
3
2
MSON
0
1
0
NESEL DTON
SA1
0
SA0
0
Initial value
Read/Write
1
0
—
—
—
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (øW) generated by the subclock pulse
generator is sampled, in relation to the oscillator clock (øOSC) generated by the system clock pulse
generator. When øOSC = 2 to 6 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0
1
Sampling rate is øOSC/16
Sampling rate is øOSC/4
(initial value)
101
ETC [ ETC ]
