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EP20K200RC208-1 参数 Datasheet PDF下载

EP20K200RC208-1图片预览
型号: EP20K200RC208-1
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列(FPGA)的\n [Field Programmable Gate Array (FPGA) ]
分类和应用: 现场可编程门阵列
文件页数/大小: 114 页 / 1501 K
品牌: ETC [ ETC ]
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APEX 20K Programmable Logic Device Family Data Sheet  
Figure 11 shows the intersection of a row and column interconnect, and  
how these forms of interconnects and LEs drive each other.  
Figure 11. Driving the FastTrack Interconnect  
Row Interconnect  
MegaLAB Interconnect  
Column  
Interconnect  
LE  
Local  
Interconnect  
APEX 20KE devices include an enhanced interconnect structure for faster  
routing of input signals with high fan-out. Column I/ O pins can drive the  
FastRow interconnect, which routes signals directly into the local  
interconnect without having to drive through the MegaLAB interconnect.  
FastRow lines traverse two MegaLAB structures. Also, these pins can  
drive the local interconnect directly for fast setup times. On EP20K300E  
and larger devices, the FastRow interconnect drives the two MegaLABs in  
the top left corner and the two MegaLABs in the bottom right corner. On  
EP20K200E and smaller devices, FastRow interconnect drives the two  
MegaLABs on the top and the two MegaLABs on the bottom of the device.  
On all devices, the FastRow interconnect drives all local interconnect in  
the appropriate MegaLABs except the interconnect areas on the far left  
and far right of the MegaLAB. Pins using the FastRow interconnect  
achieve a faster set-up time, as the signal does not need to use a MegaLab  
interconnect line to reach the destination LE. Figure 12 shows the FastRow  
interconnect.  
Altera Corporation  
23  
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