APEX 20K Programmable Logic Device Family Data Sheet
Figure 8. APEX 20K LE Operating Modes
LAB-Wide
Clock Enable (2)
Normal Mode (1)
Carry-In (3)
Cascade-In
LE-Out
LE-Out
data1
data2
PRN
D
4-Input
LUT
Q
data3
data4
ENA
CLRN
Cascade-Out
LAB-Wide
Clock Enable (2)
Arithmetic Mode
Carry-In
Cascade-In
LE-Out
LE-Out
PRN
data1
data2
D
Q
3-Input
LUT
ENA
CLRN
3-Input
LUT
Cascade-Out
Carry-Out
Counter Mode
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Synchronous
Load (6)
LAB-Wide
Clock Enable (2)
Cascade-In
Carry-In
(4)
LE-Out
data1 (5)
data2 (5)
PRN
3-Input
LUT
D
Q
LE-Out
data3 (data)
ENA
CLRN
3-Input
LUT
Carry-Out Cascade-Out
Notes:
(1) LEs in normal mode support register packing.
(2) There are two LAB-wide clock enables per LAB.
(3) When using the carry-in in normal mode, the packed register feature is unavailable.
(4) A register feedback multiplexer is available on LE1 of each LAB.
(5) The DATA1and DATA2input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
(6) The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
18
Altera Corporation
ETC [ ETC ]
