ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Note (1)
Dedicated Inputs &
Global Signals
Dedicated Clocks
Row Interconnect
RAM/ROM
2
4
4, 8, 16, 32
256 × 16
512 × 8
1,024 × 4
2,048 × 2
data[ ]
Data In
D
Q
ENA
Data Out
D
Q
4, 8
ENA
Read Address
rdaddress[ ]
D
Q
EAB Local
Interconnect (2)
ENA
wraddress[ ]
Write Address
D
Q
ENA
4, 8, 16, 32
rden
Read Enable
Write Enable
D
Q
wren
ENA
outclocken
inclocken
inclock
D
Q
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Write
Pulse
Generator
ENA
outclock
Column Interconnect
Notes:
(1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3. The
ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
10
Altera Corporation
ETC [ ETC ]
