TMS320VC5420
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS080E – MARCH 1999 – REVISED APRIL 2001
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200-MIPS Dual-Core DSP Consisting of Two
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Independent Subsystems
Each Core Has an Advanced Multibus
Architecture With Three Separate 16-Bit
Data Memory Buses and One Program Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel-Shifter and Two
40-Bit Accumulators Per Core
Each Core Has a 17-
×
17-Bit Parallel
Multiplier Coupled to a 40-Bit Adder for
Non-Pipelined Single-Cycle Multiply/
Accumulate (MAC) Operations
Each Core Has a Compare, Select, and
Store Unit (CSSU) for the Add/Compare
Selection of the Viterbi Operator
Each Core Has an Exponent Encoder to
Compute an Exponent Value of a 40-Bit
Accumulator Value in a Single Cycle
Each Core Has Two Address Generators
With Eight Auxiliary Registers and Two
Auxiliary Register Arithmetic Units
(ARAUs)
16-Bit Data Bus With Data Bus Holder
Feature
256K
×
16 Extended Program Address
Space
Total of 192K
×
16 Dual- and Single-Access
On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations
Instructions With 32-Bit Long Word
Operands
Instructions With 2 or 3 Operand Reads
Fast Return From Interrupts
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Arithmetic Instructions With Parallel Store
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and Parallel Load
Conditional Store Instructions
Output Control of CLKOUT
Output Control of TOUT
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions
Dual 1.8-V (Core) and 3.3-V (I/O) Power
Supplies for Low Power, Fast Operation
10-ns Single-Cycle Fixed-Point Instruction
Execution
Interprocessor Communication via Two
Internal 8-Element FIFOs
12 Channels of Direct Memory Access
(DMA) for Data Transfers With No CPU
Loading (6 Channels Per Subsystem)
Six Multichannel Buffered Serial Ports
(McBSPs) (Three McBSPs Per Subsystem)
16-Bit Host-Port Interface (HPI16)
Multiplexed With External Memory Interface
Pins
Software-Programmable Phase-Locked
Loop (PLL) Provides Several Clocking
Options (Requires External TTL Oscillator)
On-Chip Scan-Based Emulation Logic
Two Software-Programmable Timers
(One Per Subsystem)
Software-Programmable Wait-State
Generator (14 Wait States Maximum)
Provided in 144-pin BGA Ball Grid Array
(GGU Suffix) and 144-pin Low-Profile Quad
Flatpack (LQFP) (PGE Suffix) Packages
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NOTE:
This data sheet is designed to be used in conjunction with the
TMS320C54x DSP Functional Overview
(literature
number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C54x is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
1
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