RTL8100C & RTL8100CL
Datasheet
5.36. Config5: Configuration Register 5 (Offset 00D8h, R/W)
This register, unlike other Config registers, is not protected by the 93C46 Command register. There is no
need to enable the Config register write prior to writing to Config5.
Table 36. Config5. Configuration Register 5
Bit
7
R/W
-
Symbol
-
Description
Reserved.
6
R/W
BWF
Broadcast Wakeup Frame.
1: Enable Broadcast Wakeup Frame with Destination ID field mask
bytes of FF FF FF FF FF FF
0: Default value. Disable Broadcast Wakeup Frame with
Destination ID field mask bytes of FF FF FF FF FF FF
Multicast Wakeup Frame.
1: Enable Multicast Wakeup Frame with mask bytes of only the
Destination ID field, which is a multicast address
0: Default value. Disable Multicast Wakeup Frame with mask bytes
of only the Destination ID field, which is a multicast address
Unicast Wakeup Frame.
5
4
R/W
R/W
MWF
UWF
1: Enable Unicast Wakeup Frame with mask bytes of only the
Destination ID field, which is its own physical address
0: Default value. Disable Unicast Wakeup Frame with mask bytes of
only the Destination ID field, which is its own physical address
FIFO Address Pointer (Realtek internal use only).
The power-on default value of this bit is 0.
Link Down Power Saving mode.
3
2
R/W
R/W
FIFOAddrPtr
LDPS
1: Disable
0: Enable. When the cable is disconnected (Link Down), the analog
part will power itself down (PHY Tx part and part of the Twister)
automatically except for the PHY Rx part and the part of the twister
that monitors the SD signal in case the cable is reconnected and the
Link should be established again
1
0
R/W
R/W
LANWake
PME_STS
LANWake signal enable/disable.
1: Enable LANWake signal
0: Disable LANWake signal
PME_Status bit.
Always sticky/can be reset by PCI RST# and software.
1: The PME_Status bit may be reset by PCI reset or by software
0: The PME_Status bit may only be reset by software
Single-Chip Fast Ethernet Controller
34
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
