RTL8100C & RTL8100CL
Datasheet
5.24. PCI REVISION ID (OFFSET 005EH, R)............................................................................................28
5.25. TRANSMIT STATUS OF ALL DESCRIPTORS (TSAD) REGISTER (OFFSET 0060H-0061H, R/W).......28
5.26. BASIC MODE CONTROL REGISTER (OFFSET 0062H-0063H, R/W)..................................................29
5.27. BASIC MODE STATUS REGISTER (OFFSET 0064H-0065H, R)..........................................................29
5.28. AUTO-NEGOTIATION ADVERTISEMENT REGISTER (OFFSET 0066H-0067H, R/W).........................30
5.29. AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (OFFSET 0068H-0069H, R) ...................31
5.30. AUTO-NEGOTIATION EXPANSION REGISTER (OFFSET 006AH-006BH, R) .....................................32
5.31. DISCONNECT COUNTER ..................................................................................................................32
5.32. FALSE CARRIER SENSE COUNTER (OFFSET 006EH-006FH, R).......................................................32
5.33. NWAY TEST REGISTER (OFFSET 0070H-0071H, R/W)...................................................................33
5.34. RX_ER COUNTER (OFFSET 0072H-0073H, R)...............................................................................33
5.35. CS CONFIGURATION REGISTER (OFFSET 0074H-0075H, R/W) ......................................................33
5.36. CONFIG5: CONFIGURATION REGISTER 5 (OFFSET 00D8H, R/W)....................................................34
5.37. EEPROM (93C46) CONTENTS ......................................................................................................35
5.38. RTL8100C(L) EEPROM REGISTERS SUMMARY ..........................................................................37
5.39. EEPROM POWER MANAGEMENT REGISTERS SUMMARY ..............................................................37
6. PCI CONFIGURATION SPACE REGISTERS.............................................................................38
6.1. PCI CONFIGURATION SPACE TABLE...............................................................................................38
6.2. PCI CONFIGURATION SPACE FUNCTIONS .......................................................................................39
6.3. PCI CONFIGURATION SPACE STATUS.............................................................................................41
6.4. DEFAULT VALUES AFTER POWER-ON (RSTB ASSERTED)..............................................................44
6.5. PCI POWER MANAGEMENT FUNCTIONS.........................................................................................45
6.5.1.
Power Down Mode ..............................................................................................................45
6.6. VPD (VITAL PRODUCT DATA).......................................................................................................48
7. FUNCTIONAL DESCRIPTION......................................................................................................49
7.1. TRANSMIT OPERATION ...................................................................................................................49
7.2. RECEIVE OPERATION......................................................................................................................49
7.3. WANDER COMPENSATION ..............................................................................................................49
7.4. SIGNAL DETECT .............................................................................................................................49
7.5. LINE QUALITY MONITOR ...............................................................................................................50
7.6. CLOCK RECOVERY MODULE ..........................................................................................................50
7.7. LOOPBACK OPERATION ..................................................................................................................50
7.8. TX ENCAPSULATION.......................................................................................................................50
7.9. COLLISION......................................................................................................................................50
Single-Chip Fast Ethernet Controller
ii
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
