RTL8100C & RTL8100CL
Datasheet
5.8. Register Descriptions
The RTL8100C(L) provides the following set of operational registers mapped into PCI memory space or
I/O space.
Table 8. Register Descriptions
Offset
R/W
Tag
Description
0000h
R/W
IDR0
ID Register 0.
ID registers 0-5 are only permitted to read/write via 4-byte access.
Read access can be byte, word, or double word access. The initial
value is autoloaded from the EEPROM EthernetID field.
ID Register 1.
ID Register 2.
ID Register 3.
ID Register 4.
ID Register 5.
Reserved.
Multicast Address Register 0.
0001h
0002h
0003h
0004h
0005h
0006h-0007h
0008h
R/W
R/W
R/W
R/W
R/W
-
IDR1
IDR2
IDR3
IDR4
IDR5
-
R/W
MAR0
The MAR register 0-7 are only permitted to read/write via 4-byte
access. Read access can be byte, word, or double word access. The
driver is responsible for initializing these registers.
Multicast Address Register 1.
Multicast Address Register 2.
Multicast Address Register 3.
Multicast Address Register 4.
Multicast Address Register 5.
Multicast Address Register 6.
Multicast Address Register 7.
Transmit Status of Descriptor 0.
Transmit Status of Descriptor 1.
Transmit Status of Descriptor 2.
Transmit Status of Descriptor 3.
Transmit Start Address of Descriptor 0.
Transmit Start Address of Descriptor 1.
Transmit Start Address of Descriptor 2.
Transmit Start Address of Descriptor 3.
Receive (Rx) Buffer Start Address.
Early Receive (Rx) Byte Count Register.
Early Rx Status Register.
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h-0013h
0014h-0017h
0018h-001Bh
001Ch-001Fh
0020h-0023h
0024h-0027h
0028h-002Bh
002Ch-002Fh
0030h-0033h
0034h-0035h
0036h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
TSD0
TSD1
TSD2
TSD3
TSAD0
TSAD1
TSAD2
TSAD3
RBSTART
ERBCR
ERSR
R
0037h
0038h-0039h
003Ah-003Bh
R/W
R/W
R
CR
CAPR
CBR
Command Register.
Current Address of Packet Read.
Current Buffer Address.
The initial value is 0000h. It reflects total received byte-count in the
Rx buffer.
003Ch-003Dh
003Eh-003Fh
0040h-0043h
R/W
R/W
R/W
IMR
ISR
TCR
Interrupt Mask Register.
Interrupt Status Register.
Transmit (Tx) Configuration Register.
Single-Chip Fast Ethernet Controller
10
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
