PRELIMINARY
PCT1789W DATA SHEET
PCT789T-A PIN DESCRIPTION
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PCT789T-A PIN DESCRIPTION
Table 3 PCT789T-A Pin Description
Typ
Name
Numbers I/O
Description
e
System Bus Interface Signals
AD[31:16]
AD[15:0]
90-94,
96-98,
1-8
t/s
t/s
PCI Dual-purpose pins. Address/data bus bits [31:16]. Address and data are
multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases.
22-25,
26-28,
30-37,
40
PCI Address/data bus bits [15:0]. Address and data are multiplexed on the
same PCI pins. A bus transaction consists of an address phase fol-
lowed by one or more data phases.
C/BE[3:0]*
99,10,
20,29
t/s
I
PCI Bus command/byte enables pins. During the address phase of a trans-
action, C/BE[3:0]* define the bus command. During the data phase C/
BE[3:0]* are used as byte enables.
CLK
86
14
PCI Clock. This is a input clock signal which provides timing for all transac-
tions on PCI.
DEVSEL*
s/t/s PCI Device select. When actively driven, indicates the driving device has
decoded its address as the target of the current access. As an input,
DEVDEL* indicates whether any device on the bus has been selected.
FRAME*
GNT*
11
87
s/t/s PCI Frame. This signal is driven by the current master to indicate the begin-
ning and duration of an access. While FRAME* is asserted, data trans-
fer continues. When FRAME* is deasserted, the transaction is in the
final data phase.
t/s
PCI Grant. This signal indicates that PCT789T-A access request to the PCI
bus has been granted.
NOTE: The PCI master mode is not supported in this version, but the pin
is reserved for future expansion.
IDSEL
INTA*
IRDY*
PAR
100
83
12
19
17
88
t/s
PCI Initialization device select. This signal is active when the host wants to
do configuration read and write transactions.
OD PCI Interrupt A. This is a level sensitive output which is used to request an
interrupt by PCT789T-A.
s/t/s PCI Initiator ready. This signal indicates the initiating agent’s ability to com-
plete the current data phase of the transaction.
t/s
PCI Parity. This signal should be even parity across AD[31:00] and C/
BE[3:0]*. PAR is stable and valid one clock after the address phase.
PERR*
REQ*
s/t/s PCI Parity error. This signal is driven active when a data parity error is
detected.
t/s
PCI Request. This signal is driven when the PCT789T-A desires use of the
PCI bus.
NOTE: The PCI master mode is not supported in this version, but the pin
is reserved for future expansion.
RST*
84
15
I
ST Reset. This signal brings PCI-specific registers, sequencers, and sig-
nals to a consistent state. When active, the chip is returned to its initial
state with all the internal registers set at their default value.
STOP*
s/t/s PCI Stop. This signal indicates the current target is requesting the master to
stop the current transaction.
PRELIMINARY
PC-TEL, Inc.
10
1789W0DOCDAT06A-0299
ETC [ ETC ]
