PCT2303N DATA SHEET
CONTROL REGISTERS
!!
Chip ID and Revision
(Register 5Ah, R)
Reserved
12
CBID
REVB[3:0]
REVA[3:0]
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
Reset settings = N/A
NOTE: The line side must be activated through the PR bits before valid read.
Bit Definitions:
Bits
15:9
Name
Description
Reserved
CBID
Reserved. Read returns zero.
8
Chip B (line-side) ID.
1 = Line side has international support.
0 = Line side is domestic.
7:4
3:0
REVB[3:0]
REVA[3:0]
Chip revision. Four-bit value indicates the PCT303L (line-side) silicon revision.
Chip revision. Four-bit value indicates the PCT303A silicon revision.
Line-Side Configuration 1
(Register 5Ch, R/W)
ARM[1:0]
15 14
ATM[1:0]
13 12
IIRE
Reserved
RT
Resereved
11
10
9
8
7
6
5
4
3
2
1
0
Reset settings = F010h
Shaded bit descriptions are for international line-side support only.
Bit Definitions:
Bits
15:14
Name
Description
ARM[1:0]
Analog (call progress) receive path mute.
ARM[1:0]
Description
00
01
10
11
0dB
–6dB
–12dB
Mute
13:12
ATM[1:0]
Analog (call progress) transmit path mute.
ARM[1:0]
Description
00
01
10
11
0dB
–6dB
–12dB
Mute
11
IIRE
IIR filter enable.
1 = Transmit and receive filters are realized with an IIR filter characteristic.
2:1
Reserved
Reserved. Read returns zero.
PC-TEL, Inc.
24
2303N0DOCDAT10A-0899
ETC [ ETC ]
