2.17 Byte to Symbol Conversion
2-25
2-26
2-27
2-29
2-34
2-36
2-38
2-40
3-4
2.18 Differential Encoder and QAM Mapping
2.19 Pulse Shaper Structure
2.20 Output Scaling by Arithmetic Shift Right
2.21 Square-Root Raised Cosine Filter
2.22 NCO Loop Diagram
2.23 Frequency Acquisition Loop Overview
2.24 Serial Bus Base Address
3.1
3.2
5.1
6.1
6.2
6.3
6.4
6.5
A.1
A.2
A.3
A.4
A.5
B.1
B.2
Analog I/Q Output Interface Diagram
I And Q DAC Filter Diagrams
Logic Symbol for the L64777
TS Input Timing
3-5
5-2
6-3
L64777 RESET Timing Diagram
L64777 Bus 3-state Delay Timing
Package 120-Pin PQFP Pinout
120-Pin PQFP (PE) Mechanical Drawing
Quick Overview of the Serial Bus
Serial Bus Write/Read Cycle
6-3
6-4
6-10
6-11
A-2
A-3
General Call Structure
A-4
Burst Write to Slave (Master-Transmitter, Slave-Receiver)
Single Read from Slave
A-5
A-7
CATV Block Diagram
B-1
Signals between the L64724 and L64777
B-3
Tables
2.1
2.2
4.1
4.2
6.1
6.2
6.3
6.4
6.5
6.6
6.7
B.1
Allocation of Coefficient-Bits for Phase 0
Default Nyquist Filter Coefficients
Group 2 Bit Allocation
2-30
2-32
4-2
Reset Values for Register Fields
L64777 Absolute Maximum Ratings
L64777 Recommended Operating Conditions
L64777 DC Characteristics
4-17
6-2
6-2
6-2
L64777 Preliminary Timing Parameters
L64777 Pin Description Summary
L64777 Numerical Pin List
6-4
6-5
6-8
L64777 Alphabetical Pin List
6-9
Typical Settings of CNT_I and CNT_O
B-2
Contents
ix
ETC [ ETC ]
