Appendix C
Monitoring Device
Internal Signals
The programming of the test register (14) allows monitoring of the
device’s internal signals. Depending on the programming of the test
register bits (Register 15), the following signals are observable on the
DIG_Q[9:0] pins:
TEST[3:0]
0b0000:
0b0001:
0b0010:
0b0011:
Nyquist filter output or interpolator output (normal operation)
FIFO output
Scrambler output
RS encoder output
0b0100:
0b0101:
0b0110:
0b0111:
Interleaver output
M-tuple output
Mapper output
N/A
0b1000:
0b1001:
0b1010:
0b1011:
Interpolator control
NCO step bit [23:16] on DIG_Q[7:0]
NCO step bit [15:8] on DIG_Q[7:0]
NCO step bit [7:0] on DIG_Q[7:0]
0b1100:
0b1101:
0b1110:
0b1111:
Virtual FIFO content
Value reserved; do not program
Value reserved; do not program
Value reserved; do not program
test.4:
test.5:
test.6:
Set to 1 for power-down mode; after reset, this is 0
Set to 1 for power-down mode; after reset, this is 0
Set to 1 for power-down mode; after reset, this is 0
L64777 DVB QAM Modulator Technical Manual
C-1
ETC [ ETC ]
