TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
9.15.11 Evaluating Echo Canceller Performance
The CT8022 AEC uses a pair of VOX detectors to detect the presence of speech and to control the operation of the
echo canceller and echo suppressor. These detectors respond to short-term rates of change in signal energy. This
enables the detectors to distinguish between real voice activity and background noise. Therefore, it is not
appropriate to test CT8022 AEC performance using continuous sine waves. The CT8022 should only be tested using
real speech or alternatively using pulsed (dual) sine waves or pulsed white noise. The pulse duration should typically
be less than 500ms.
9.16
Speech Frame Interrupt
The CT8022 can provide a speech frame-by-frame interrupt from the TX READY and RX READY signals of the
Hardware Status Register. For added flexibility two additional mechanisms are provided for generating interrupts
derived from the frame rate.
9.16.1
Frame Interrupt via the FR Pin
For compatibility with the CT8015, the CT8022 can provide a Frame Interrupt signal via the FR/ pin GPIO5. For
the CT8022, by default, this pin is not enabled, and GPIO5 is configured as an input. Refer to Section 9.25 for
instructions on enabling FR pin functionality.
If the FR/ pin functionality is enabled, then when record, playback or full-duplex speech mode is active, the FR/ pin
is asserted (driven low) every frame period. This makes the FR/ signal useful as a frame interrupt to the Host. Since
FR/ is asserted every frame period, a new record frame will be available to the Host in the receive frame buffer, or a
space will be available for a new playback frame in the transmit frame buffer, each time the FR/ is asserted. The
Host can clear the FR/ signal using the CLEAR FR command:
The FR/ pin is implemented using the GPIO 5 pin. This is an optional signal provided for CT8015 TrueSpeech
DSVD Co-Processor compatibility. If this pin is not required, the GPIO 5 pin is available for general-purpose use.
Instead of using the FR/ pin, the Host can use the IRQN interrupt pin and enable it to be driven from the
transmit/receive data buffer TX or RX READY signal by programming the Hardware Control Register. This will
then provide an interrupt each time a compressed data frame is ready (30ms). The interrupt is cleared by filling or
emptying the data buffer as appropriate.
The following commands are available for controlling the FR/ pin: Enable, Disable, Clear and Read.
Enable FR:
Command: 5141H
Status:
5141H
by default, the FR pin is enabled.
Disable FR:
Command: 5142H
Status:
5142H
118
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
