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CT8022A11AQC 参数 Datasheet PDF下载

CT8022A11AQC图片预览
型号: CT8022A11AQC
PDF下载: 下载PDF文件 查看货源
内容描述: VOIP / VON G.723.1 , G279AB TRUESPEECH协处理器 [VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR]
分类和应用:
文件页数/大小: 194 页 / 1455 K
品牌: ETC [ ETC ]
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TrueSpeech® Co-Processor  
PRELIMINARY/CONFIDENTIAL  
Version: 1.18  
If the speech frame is 240 and the AEC adaptation limit is set to 120, the peak adaptation processing load is reduced  
by 50% and the AEC adaptation (training) time is doubled. If the limit is set to 60, then the load is reduced by 25%,  
and the adaptation (training) time is quadrupled.  
The following command sequences can be used to program the AEC adaptation limits:  
To set the maximum AEC adaptation limit:  
C1  
S1  
C2  
S2  
E02CH  
E02CH  
00XXH  
00XXH  
Where XX is the adaptation limit  
To set the minimum AEC adaptation limit:  
C1  
S1  
C2  
S2  
E02DH  
E02DH  
00XXH  
00XXH  
Where XX is the adaptation limit  
9.15.3.1  
Reading the CT8022 DSP Processor Load  
The Host can check if the CT8022 DSP Processor is being over-committed by polling the DSP processor load for the  
current speech frame.  
Command:  
Status  
511BH  
load-value  
When the load value returned is 0, the DSP processor is 100% loaded.  
The load value is measured by counting the number of internal CODEC interrupts that the DSP receives when it is an  
internal idle loop waiting for availability of the next speech frame to process. When this value reaches zero, it  
indicates that as soon as the DSP code reaches the idle loop, it finds that the next speech frame is immediately  
available for processing.  
The maximum value read (lowest amount of load) depends upon the speech frame size and the 8/16-bit CODEC  
configuration. In 8-bit mode, the CODEC generates a single interrupt for every two 8-bit CODEC samples. With an  
8.0 KHz CODEC fsync rate, a CODEC interrupt is generated every 250 µs. In 16-bit mode, the CODEC interrupt is  
generated for each sample, once every 125 µs.  
In 8-bit CODEC mode, with a 30ms speech frame, there will be 120 CODEC interrupts per speech frame, so that the  
DSP processor load can be calculated as:  
(1 - load-value/120) * 100%  
In 16-bit mode with a 10ms speech frame, there will be 80 CODEC interrupts per speech frame, so that the DSP load  
is:  
(1 - load-value/80) * 100%  
In both cases, a load value of zero indicates the DSP processor is 100% loaded. At this load level, the DSP may start  
to drop speech frames.  
The load level is only meaningful in Host-to-CODEC mode. It is not valid in Host-to-Host mode.  
104  
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118  
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490  
All specifications are subject to change without prior notice.  
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