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VS1003 参数 Datasheet PDF下载

VS1003图片预览
型号: VS1003
PDF下载: 下载PDF文件 查看货源
内容描述: MP3 / WMA音频编解码器 [MP3 / WMA AUDIO CODEC]
分类和应用: 解码器编解码器
文件页数/大小: 57 页 / 454 K
品牌: ETC [ ETC ]
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VS1003  
VLSI  
VS1003 PRELIMINARY  
y
Solution  
5. PACKAGES AND PIN DESCRIPTIONS  
5.2 LQFP-48 and BGA-49 Pin Descriptions  
Pin Name  
LQFP- BGA49 Pin  
48 Pin Ball Type  
Function  
MICP  
MICN  
1
2
3
4
5
6
7
8
9
C3  
C2  
B1  
D2  
C1  
D3  
D1  
E2  
E1  
F2  
AI  
AI  
DI  
DGND  
CPWR  
IOPWR  
CPWR  
DO  
Positive differential microphone input, self-biasing  
Negative differential microphone input, self-biasing  
Active low asynchronous reset  
Core & I/O ground  
Core power supply  
I/O power supply  
Core power supply  
Data request, input bus  
General purpose IO 2 / serial input data bus clock  
General purpose IO 3 / serial data input  
XRESET  
DGND0  
CVDD0  
IOVDD0  
CVDD1  
DREQ  
GPIO2 / DCLK1  
GPIO3 / SDATA1 10  
XDCS / BSYNC1 13  
DIO  
DIO  
E3  
F3  
G2  
F4  
G3  
E4  
G4  
F5  
DI  
IOPWR  
DO  
DGND  
AO  
AI  
IOPWR  
IOPWR  
DGND  
DGND  
DGND  
DI  
Data chip select / byte sync  
I/O power supply  
Clock VCO output  
Core & I/O ground  
Crystal output  
Crystal input  
I/O power supply  
I/O power supply  
Core & I/O ground  
Core & I/O ground  
Core & I/O ground  
Chip select input (active low)  
Core power supply  
IOVDD1  
VCO  
14  
15  
16  
17  
18  
19  
DGND1  
XTALO  
XTALI  
IOVDD2  
IOVDD3  
DGND2  
DGND3  
DGND4  
XCS  
20  
21  
22  
23  
24  
G5  
F6  
G6  
G7  
CVDD2  
CPWR  
RX  
TX  
SCLK  
SI  
SO  
CVDD3  
TEST  
GPIO0 / SPIBOOT 33  
26  
27  
28  
29  
30  
31  
32  
E6  
F7  
D6  
E7  
D5  
D7  
C6  
C7  
DI  
DO  
DI  
UART receive, connect to IOVDD if not used  
UART transmit  
Clock for serial bus  
Serial input  
Serial output  
DI  
DO3  
CPWR  
DI  
Core power supply  
Reserved for test, connect to IOVDD  
General purpose IO 0 / SPIBOOT, use 100 k pull-down  
resistor2  
DIO  
GPIO1  
34  
B6  
DIO  
General purpose IO 1  
AGND0  
AVDD0  
RIGHT  
AGND1  
AGND2  
GBUF  
AVDD1  
RCAP  
AVDD2  
LEFT  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
C5  
B5  
A6  
B4  
A5  
C4  
A4  
B3  
A3  
B2  
A2  
A1  
APWR  
APWR  
AO  
APWR  
APWR  
AO  
APWR  
AIO  
APWR  
AO  
Analog ground, low-noise reference  
Analog power supply  
Right channel output  
Analog ground  
Analog ground  
Ground buffer  
Analog power supply  
Filtering capacitance for reference  
Analog power supply  
Left channel output  
Analog ground  
AGND3  
LINEIN  
APWR  
AI  
Line input  
1 First pin function is active in New Mode, latter in Compatibility Mode.  
2 Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.4 for details.  
Version 0.92, 2005-06-07  
13