VS1001K
VLSI
DATASHEET
y
Solution
9. WRITING SOFTWARE
Instruction (32−bit)
X (16−bit)
Y (16−bit)
Stack
Stack
0000
0000
0097
0097
User
Space
0780
07FF
0780
07FF
User
Space
1380
13FF
1380
13FF
System Vectors
4000
4000
4020
4020
User
Instruction
Space
Hardware
Registers
43FF
43FF
8000
8020
8000
Instruction
Shadow
Memory
Instruction 8020
Shadow
Memory
MSBs
LSBs
83FF
83FF
Figure 12: User’s Memory Map.
9.4.3 DAC Registers, 0x4200
DAC data should be written at each audio interrupt to DAC LEFT (0x4200) and DAC RIGHT (0x4201)
as signed values. INT FCTLL (0x4202) is not a user-serviceable register.
9.4.4 Interrupt Registers, 0x4300
INT ENABLE (0x4300) controls the interrupts. Bit 0 switches the DAC interrupt on (1) and off (0), bit 1
controls the SCI interrupt, and bit 2 controls the DATA interrupt. It may take upto 6 clock cycles before
changing this register has any effect.
By writing any value to INT GLOB DIS (0x4301) adds one to the interrupt counter and effectively
disables all interrupts. It may take upto 6 clock cycles before writing this register has any effect.
Writing any value to INT GLOB ENA (0x4302) subtracts one from the interrupt counter. If the interrupt
counter becomes zero, interrupts selected with INT ENABLE are restored. An interrupt routine should
always write to this register as the last thing it does, because interrupts automatically add one to the
interrupt counter, but subtracting it back to its initial value is on the responsibility of the user. It may take
upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER (0x4303) the user may check if the interrupt counter is correct or not. If the
register is not 0, interrupts are disabled. This register may not be written to.
Version 4.11, 2003-09-18
33
ETC [ ETC ]
