VS1001K
VLSI
DATASHEET
y
Solution
8. OPERATION
8 Operation
8.1 Clocking
The VS1001k chip operates typically on a single 24.576 MHz fundamental frequency master clock. This
clock can be generated by external circuitry (connected to pin XTALI) or by the internal clock chrystal
interface (pins XTALI and XTALO). This clock is sufficient to support a high quality audio output for
almost all the standard sample rates and bit-rates (see Application Notes for VS10XX).
Note: Oscillators above 24.576 MHz are usually so-called
harmonic clocks, which have a fundamen-
tal frequency of 1/3 of the nominal clock frequency. With such an oscillator, VS1001 would be running at
the base frequency, if working at all. Thus, for instance, if you run VS1001 with a 32 MHz
clock, you usually end up running the chip at 32 MHz / 3 = 10.67 MHz.
harmonic
8.2 Powerdown
In powerdown mode the chip only monitors the control bus. The analog output drivers are turned off and
the processor remains in hold-state.
8.3 Hardware Reset
When the XRESET -signal is driven low, VS1001k is reset and all the control registers and internal
states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1001k are in minimum
power consumption stage, and where clocks are stopped. Also XTALO and XTALI are grounded.
After a hardware reset (or at power-up), set the basic software registers such as VOL for volume (and
CLOCKF if the input clock is anything else than 24.576 MHz) before starting decoding.
8.4 Software Reset
Between any two MP3 files, the decoder software has to be reset. This is done by activating bit 2 in SCI’s
MODE register (Chapter 7.5.1). Then wait for at least 2 s, then look at DREQ. DREQ will stay down
for at least 6000 clock cycles, which means an approximate 250 s delay if VS1001k is run at 24.576
MHz. When DREQ goes up, write at least one zero to SDI. After this, you may continue playback as
usual.
If you want to make sure VS1001k doesn’t cut the ending of low-bitrate data streams, it is recommended
to feed 2048 zeros to the SDI bus before activating the reset bit (DREQ must be respected just as with
normal SDI data). This will make sure all frames have been decoded before resetting the chip.
Version 4.11, 2003-09-18
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