ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Note (1)
Row Interconnect
2
4
data[ ]
D
ENA
Q
RAM/ROM
256
×
16
512
×
8
Data In
1,024
×
4
2,048
×
2
Data Out
D
ENA
Q
4, 8, 16, 32
4, 8
rdaddress[ ]
EAB Local
Interconnect (2)
wraddress[ ]
D
Q
Read Address
D
ENA
Q
Write Address
ENA
rden
wren
outclocken
4, 8, 16, 32
Read Enable
D
ENA
Q
Write Enable
inclocken
D
ENA
Q
inclock
outclock
Write
Pulse
Generator
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Column Interconnect
Notes:
(1)
(2)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in
Figure 3.
The
ACEX 1K EAB can also be used in a single-port mode (see
Figure 4).
10
Altera Corporation
ETC [ ETC ]
