CXD3018Q/R
§4-10. DAC Block Input Timing
Timing Chart 4-12 shows the DAC block input timing chart.
In the CXD3018Q/R, the data can be transferred from the CD signal processor block to the DAC block via the
outside of the LSI. This allows the data to be sent to the DAC block via the audio DSP, etc.
As for the data input to the DAC block without using the audio DSP, there are two methods: one is to connect
directly EMPH, LRCK, BCK and PCMD with EMPHI, LRCKI, BCKI and PCMDI outside the LSI; and the other
is to set OUTL0 of $8X to 1. Note that the outputs of EMPH, LRCK, BCK and PCMD become low when OUTL0
of $8X is set to 0 .
§4-11. Description of DAC Block Functions
Zero data detection
When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently
for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected with the ZDPL command of $9X.
• When zero data is detected
• When a high signal is input to the SYSM pin
• When the SMUT command of $AX is set
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3
(Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches
Y3 from the value (B or C in the figure) at that point.
0dB
7F (H)
A
Y1
B
Y3
C
Y2
– ∞
00 (H)
23.2 [ms]
– 78 –
ETC [ ETC ]
