CXD3018Q/R
Anti Shock fs = 88.2kHz
2 – 1
M08
TRK
M09
Z – 1
M0A
Z – 1
Anti Shock
Reg
Comp
K12
K35
In Reg
Z – 1
K16
K33
K34
K31
2 – 7
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator level is 1/16 the maximum amplitude of the comparator input.
AVRG fs = 88.2kHz
2 – 1
2 – 7
M08
VC, TE, FE,
RFDC
AVRG Reg
Z – 1
TRK Hold fs = 345Hz
TRK SERVO FILTER
Second-stage output
K46
THSK (only when TGup2 is used)
M0D
THID
M18
Z – 1
M19
Z – 1
TRK
Hold Reg
K45
2 – 1
K40
SLD
In Reg
K41
K43
K44
2 – 7
2 – 7
K42
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS Hold fs = 345Hz
FCS SERVO FILTER
First-stage output
M1F
M1E
K2B when using the
FCS Gain Down filter
K2B
K0F
DFIS
($3E)
M04
M10
Z – 1
M11
Z – 1
M12
FCS
Hold Reg 2
K48
K4D
M05
FCS SERVO FILTER
Second-stage output
K49
K4B
K4C
2 – 7
2 – 7
K4A
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
– 131 –
ETC [ ETC ]
