CXD3018Q/R
$34E (preset: $34E000)
D15 D14 D13 D12 D11 D10 D9
D8
D7
0
D6
0
D5
D4
D3
0
D2
0
D1
0
D0
1
1
1
0
IDFSL3 IDFSL2 IDFSL1 IDFSL0
IDFT1 IDFT0
INVRFDC
IDFSL3:
New DFCT detection output setting.
When 0, only the DFCT signal described in §5-9 is detected and output from the DFCT pin.
(default)
When 1, the DFCT signal described in §5-9 and the new DFCT signal are switched and output
from the DFCT pin.
The switching timing is as follows.
When the §5-9 DFCT signal is low, the new DFCT signal is output from the DFCT pin.
When the §5-9 DFCT signal is high, this DFCT signal is output from the DFCT pin.
In addition, the time at which the new DFCT signal can be output after the §5-9 DFCT signal
switches to low can also be set. (See IDFT1, 0 of $34E.)
IDFSL3
DFCT pin
§5-9 DFCT
§5-9 DFCT
0
0
1
1
L
H
L
§5-9 DFCT
New DFCT
§5-9 DFCT
H
IDFSL2:
New DFCT detection time setting.
DFCT = high is held for a certain time after new DFCT detection. This command sets that time.
When 0, a long hold time. (default)
When 1, a short hold time.
IDFSL1:
IDFSL0:
IDFT1, 0:
New DFCT detection sensitivity setting.
When 0, a high detection sensitivity. (default)
When 1, a low detection sensitivity.
New DFCT release sensitivity setting.
When 0, a high release sensitivity. (default)
When 1, a low release sensitivity.
These commands set the time at which the new DFCT signal can be output (output prohibited
time) after the §5-9 DFCT signal switches to low.
IDFT1
New DFCT signal output prohibited time
IDFT0
0
0
1
1
204.08µs
294.78µs
408.16µs
612.24µs
: preset
0
1
0
1
INVRFDC:
RFDC signal polarity inverted input setting.
When 0, the RFDC signal polarity is set to non-inverted. (default)
When 1, the RFDC signal polarity is set to inverted.
– 106 –
ETC [ ETC ]
