CXA1782CQ/CR
Block Diagram
36
35
34
33
32
31
30
29
28
27
26
25
APC
LEVEL S
SENS
24
I IL
23 C.OUT
TTL
RF IV AMP1
22 XRST
21 DATA
MIRR
FOK
DFCT
TTL
I IL
RF IV AMP2
37
38
FE_BIAS
•I IL DATA REGISTER •INPUT SHIFT REGISTER
•ADRESS.DECODER
TTL
XLT
CLK
20
19
FE AMP
I IL
F
•OUTPUT DECODER
F IV AMP
E IV AMP
39
40
TOG1 to 3
BAL1 to 3
E
FS1 to 4 TG1 to 2 TM1 to 7 PS1 to 4
FZC COMP
Vcc
18
EI
TE AMP
•TRACKING
PHASE COMPENSATION
HPF COMP LPF COMP
ISET
•I SET
17
16
TM6
VEE 41
SL_O
TEO 42
TG1
TM5
TM4
15 SL_M
TZC COMP
LPFI 43
TEI 44
14 SL_P
13 TA_O
•FCS PHASE COMPENSATION
FS1
TM2
DFCT
TM1
TM3
TM7
•WINDOW COMP.
ATSC
ATSC 45
46
TZC
FS2
TDFCT 47
TG2
DFCT
48
VC
FS4
1
2
3
4
5
6
7
8
9
10
11
12
• The switch state in Block Diagram is for initial resetting.
• Switch turns to side for 1 and to• side for 0 in Serial Data Truth Table.
°
• DFCT switch turns to side when defect signal generates for DEFECT = E in Serial Data Truth Table.
°
• TG1 switch turns to side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.
°
– 2 –
ETC [ ETC ]
