Contents
4
ARM Instruction Set
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
Instruction Set Summary
The Condition Field
Branch and Exchange (BX)
Branch and Branch with Link (B, BL)
Data Processing
PSR Transfer (MRS, MSR)
Multiply and Multiply-Accumulate (MUL, MLA)
Single Data Transfer (LDR, STR)
Halfword and Signed Data Transfer
Block Data Transfer (LDM, STM)
Single Data Swap (SWP)
Software Interrupt (SWI)
Coprocessor Data Operations (CDP)
Coprocessor Data Transfers (LDC, STC)
Coprocessor Register Transfers (MRC, MCR)
Undefined Instruction
Instruction Set Examples
4-1
4-2
4-5
4-6
4-8
4-10
4-18
4-23
4-28
4-34
4-40
4-47
4-49
4-51
4-53
4-57
4-60
4-61
Multiply Long and Multiply-Accumulate Long (MULL,MLAL) 4-25
Open Access
4.16
4.17
4.18
5
THUMB Instruction Set
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
Format 1: move shifted register
Format 2: add/subtract
Format 3: move/compare/add/subtract immediate
Format 4: ALU operations
Format 5: Hi register operations/branch exchange
Format 6: PC-relative load
Format 7: load/store with register offset
Format 8: load/store sign-extended byte/halfword
Format 9: load/store with immediate offset
Format 10: load/store halfword
Format 11: SP-relative load/store
Format 12: load address
Format 13: add offset to Stack Pointer
Format 14: push/pop registers
Format 15: multiple load/store
Format 16: conditional branch
Format 17: software interrupt
5-1
5-5
5-7
5-9
5-11
5-13
5-16
5-18
5-20
5-22
5-24
5-26
5-28
5-30
5-32
5-34
5-36
5-38
Contents-ii
ARM7TDMI Data Sheet
ARM DDI 0029E
ETC [ ETC ]
