SWITCHING SPECIFICATIONS AT T
A
= 25°C ( V
CC
= 5V, I
F
= 7.5mA Unless otherwise noted )
PARAMETER
Propagation Delay Time
to Logic Low at Output
( fig 1 )( note4 )
Propagation Delay Time
to Logic High at Output
( fig 1 )( note5 )
Propagation Delay Time
of Enable from V
EH
to V
EL
( note6 )
Propagation Delay Time
of Enable from V
EL
to V
EH
( note7 )
Common Mode Transient
Immunity at Logic High
Level Output ( fig 2 )( note8 )
Common Mode Transient
Immunity at Logic Low
Level Output ( fig 2 )( note9 )
SYM DEVICE
t
PHL
MIN TYP MAX UNITS TEST CONDITION
55
75
ns
R
L
= 350
Ω,
C
L
= 15pF
t
PLH
45
75
ns
R
L
= 350
Ω,
C
L
= 15pF
t
EHL
14
ns
R
L
= 350
Ω,
C
L
= 15pF
V
EL
= 0V, V
EH
= 3V
R
L
= 350
Ω,
C
L
= 15pF
V
EL
= 0V, V
EH
= 3V
I
F
= 0mA, V
CM
= 50V
PP
R
L
= 350
Ω,
V
OH
= 2Vmin.
V
CM
= 50V
PP
R
L
=350
Ω,
V
OL
=0.8Vmax.
t
ELH
25
ns
CM
H
6N137
ICPL2601
10000
1000 10000
V/
µ
s
V/
µ
s
V/
µ
s
V/
µ
s
CM
L
6N137
-10000
ICPL2601 -1000 -10000
NOTES:-
1
Bypassing of the power supply line is required, with a 0.01
µ
F ceramic disc capacitor adjacent to
each isolator. The power supply bus for the isolator(s) should be seperate from the bus for any
active loads. Otherwise a larger value of bypass capacitor (up to 0.1
µ
F) may be needed to supress
regenerative feedback via the power supply.
2
Peaking circuits may produce transient input currents up to 50mA, 50ns maximum pulse width,
provided average current does not exceed 20mA.
3
Device considered a two terminal device; pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7
and 8 shorted together.
4
The t
PHL
propagation delay is measured from the 3.75 mA level Low to High transition of the input
current pulse to the 1.5V level on the High to Low transition of the output voltage pulse.
5
The t
PLH
propagation delay is measured from the 3.75mA level High to Low transition of the input
current pulse to the 1.5V level on the Low to High transition of the output voltage pulse.
6
The t
EHL
enable input propagation delay is measured from the 1.5V level on the Low to High transition of
the enable input voltage pulse to the 1.5V level on the High to Low of the output voltage pulse.
7
The t
ELH
enable input propagation delay is measured from the 1.5V level on the High to Low transition of
the enable input voltage pulse to the 1.5V level on the Low to High of the output voltage pulse.
8
CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output
will remain in a high logic state (ie Vout > 2.0V).
9
CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output
will remain in a low logic state (ie Vout < 0.8V)
10
No external pull up is required for a high logic state on the enable input.
FIG.1 SWITCHING TEST CIRCUIT
PULSE
GENERATOR
Z
O
= 50
Ω
t
r
= 5ns
5V
1.5V
t
PHL
t
PLH
1.5V
V
OL
10% Duty Cycle
1/f < 100
µ
s
I
F
1
2
3
8
7
6
5
C
L
= 15pF
DB91063-AAS/A1
I
F
V
O
0
5V
R
L
V
O
I
F
Monitor
100
Ω
4
19/4/99
ETC [ ETC ]
