Z8FMC16100 Series Flash MCU
Product Specification
247
resumes executing and it will not be decremented when the CPU is running. A BRK will
be generated when the program counter matches the value in the OCDCNTR register
before executing the instruction at the location of the program counter.
The OCDCNTR register is used by many of the OCD commands. It counts the number
of bytes for the register and memory read/write commands. It retains the residual value
when generating the CRC. If the OCDCNTR is used to generate a BRK, its value must
be written as a final step before leaving DEBUG mode.
Caution:
Because this register is overwritten by various OCD commands, it must only be used to
generate temporary break points, such as stepping over CALL instructions or running to a
specific instruction and stopping.
When the OCDCNTR register is read, it returns the inverse of the data in this register. The
OCDCNTR register is only decremented when counting. The mode where it counts the
number of clock cycles in between execution is achieved by counting down from its max-
imum count. When the OCDCNTR register is read, the counter appears to have counted
up because its value is inverted. The value in this register is always inverted when it is
read. If this register is used as a hardware break point, the value read from this register will
be the inverse of the data actually in the register.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In Debug mode, all OCD commands become available unless the user code is pro-
tected by programming the Read Protect option bit (RP). The Read Protect option bit
prevents the code in memory from being read out of the Z8FMC16100 Series Flash MCU
device. When this option is enabled, several of the OCD commands are disabled. Table
134 contains a summary of the On-Chip Debugger commands. Each OCD command is
described in further detail in the bulleted list following Table 134. Table 134 indicates
those commands that operate when the device is not in DEBUG mode (normal operation)
and those commands that are disabled by programming the Read Protect option bit.
Table 134. On-Chip Debugger Commands
Command
Byte
Enabled When Not
In Debug Mode?
Disabled by Read Protect
Option Bit
Debug Command
Read Revision
00h
01h
02h
03h
Yes
—
—
—
—
—
Write OCD Counter Register
Read OCD Status Register
Read OCD Counter Register
Yes
—
PS024604-1005
P R E L I M I N A R Y
On-Chip Debugger Commands
ZILOG [ ZILOG, INC. ]
