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Z8FMC04100QKSG 参数 Datasheet PDF下载

Z8FMC04100QKSG图片预览
型号: Z8FMC04100QKSG
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采-R电机控制闪存MCU [Z8 Encore-R Motor Control Flash MCUs]
分类和应用: 闪存微控制器和处理器外围集成电路电机时钟
文件页数/大小: 402 页 / 4558 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore!® Motor Control Flash MCUs  
Product Specification  
234  
Bit  
Value  
(H)  
Description  
Position  
[7]  
Internal Precision Oscillator Enable  
Internal precision oscillator is disabled.  
INTEN  
0
1
Internal precision oscillator is enabled.  
[6]  
Crystal Oscillator Enable  
XTLEN  
0
1
Crystal oscillator is disabled.  
Crystal oscillator is enabled.  
[5]  
Watch-Dog Timer Oscillator Enable  
Watch-Dog Timer oscillator is disabled  
WDTEN  
0
1
Watch-Dog Timer oscillator is enabled  
[4]  
Primary Oscillator Failure Detection Enable  
POFEN  
0
1
0
1
Failure detection and recovery of primary oscillator is disabled. This bit is cleared  
automatically if a primary oscillator failure is detected.  
Failure detection and recovery of primary oscillator is enabled  
[3]  
Watch-Dog Timer Oscillator Failure Detection Enable  
WDFEN  
Failure detection of Watch-Dog Timer oscillator is disabled.This bit is cleared  
automatically if a Watch-Dog Timer oscillator failure is detected.  
Failure detection of Watch-Dog Timer oscillator is enabled  
[2]  
Flash Low Power Mode Enable  
FLPEN  
0
1
Flash Low Power Mode is disabled.  
Flash Low Power Mode is enabled. The Flash will be powered down during idle  
periods of the clock and powered up during Flash reads. This bit should only be  
set if the frequency of the primary oscillator source is 8MHz or lower. The reset  
value of this bit is controlled by the LPDENoption bit during reset.  
[1:0]  
System Clock Oscillator Select  
SCKSEL  
00  
01  
10  
11  
Internal precision oscillator functions as system clock at 5.6 MHz  
Crystal oscillator or external clock driver functions as system clock  
Reserved  
Watch-Dog Timer oscillator functions as system clock  
Oscillator Divide Register  
The Oscillator Divide Register (OSCDIV) provides the value that divides the system  
clock. The Oscillator Divide Register must be unlocked before writing. Writing the two-  
step sequence E7h,followed by 18h, to the Oscillator Control Register address unlocks  
the register. The register locks after completion of a register Write to the OSCDIV.  
Oscillator Control  
P R E L I M I N A R Y  
PS024604-1005  
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