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Z8FMC04100QKSG 参数 Datasheet PDF下载

Z8FMC04100QKSG图片预览
型号: Z8FMC04100QKSG
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采-R电机控制闪存MCU [Z8 Encore-R Motor Control Flash MCUs]
分类和应用: 闪存微控制器和处理器外围集成电路电机时钟
文件页数/大小: 402 页 / 4558 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8FMC16100 Series Flash MCU  
Product Specification  
101  
Compare Mode  
In COMPARE mode, the timer counts up to the 16-bit compare value stored in the Timer  
Reload High and Low Byte registers. After reaching the compare value, the timer gener-  
ates an interrupt and counting continues (the timer value is not reset to 0001h). If the  
Timer Output alternate function is enabled, the Timer Output pin changes state (from Low  
to High or from High to Low).  
If the timer reaches FFFFh, the timer rolls over to 0000hand continues counting.  
The steps for configuring a timer for COMPARE mode and initiating the count are as fol-  
lows:  
1. Write to the Timer Control registers to:  
a. Disable the timer.  
b. Configure the timer for COMPARE mode.  
c. Set the prescale value.  
d. Set the initial logic level (High or Low) for the Timer Output alternate function, if  
appropriate.  
2. Write to the Timer High and Low Byte registers to set the starting count value.  
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.  
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing  
to the relevant interrupt registers.  
5. If using the Timer Output function, configure the associated GPIO port pin for the  
Timer Output alternate function.  
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.  
The compare time is calculated by the following equation (Start Value is typically = 1):  
(Compare Value – Start Value +1) x Prescale  
Compare Mode Time (s) =  
System Clock Frequency (Hz)  
Gated Mode  
In GATED mode, the timer counts only when the Timer Input signal is in its active state,  
as determined by the TPOLbit in the Timer Control 1 Register. When the Timer Input sig-  
nal is active, counting begins. A timer interrupt is generated when the Timer Input signal  
transitions from active to inactive state, a timer reload occurs, or both, depending on  
TICONFIG[1:0]. To determine if a Timer Input signal deassertion generated the inter-  
rupt, read the associated GPIO input value and compare it to the value stored in the TPOL  
bit.  
PS024604-1005  
P R E L I M I N A R Y  
Timer Operating Modes  
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