Z8FMC16100 Series Flash MCU
Product Specification
99
If TPOLis set to 0, the ratio of the PWM output High time to the total period is determined
by the equation:
Reload Value – PWM Value
PWM Output High Time Ratio (%) =
x 100
Reload Value
If TPOLis set to 1, the ratio of the PWM output High time to the total period is determined
by the equation:
PWM Value
PWM Output High Time Ratio (%) =
x 100
Reload Value
Capture Modes
There are three capture modes that provide slightly different methods for recording the
time of, or time interval between, Timer Input events. These modes are CAPTURE mode,
CAPTURE RESTART mode, and CAPTURE COMPARE mode. In all three modes, when
the appropriate Timer Input transition (capture event) occurs, the timer counter value is
captured and stored in the PWM High and Low Byte registers. The TPOLbit in the Timer
Control 1 Register determines whether the Capture occurs on a rising edge or a falling
edge of the Timer Input signal. The TICONFIGbit determines whether interrupts are gen-
erated on capture events, reload events, or both. The INCAPbit in Timer Control 0 Regis-
ter clears to indicate an interrupt caused by a reload event and sets to indicate the timer
interrupt is caused by an input capture event.
There is a delay from the input event to the timer capture of 2–3 system clock cycles, due
to internal synchronization logic.
If the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reload. The initial value is determined
by the TPOLbit.
Capture Mode. In CAPTURE mode, and after it is enabled, the timer counts continuously
and rolls over from FFFFhto 0000h. When the capture event occurs, the timer counter
value is captured and stored in the PWM High and Low Byte registers, an interrupt is gen-
erated, and the timer continues counting. The timer continues counting up to the 16-bit
reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the
reload value, the timer generates an interrupt and continues counting.
Capture Restart Mode. In CAPTURE RESTART mode, after it is enabled, the timer
counts continuously until either the capture event occurs or the timer count reaches the 16-
bit compare value stored in the Timer Reload High and Low Byte registers. If the capture
event occurs first, the timer counter value is captured and stored in the PWM High and
Low Byte registers, an interrupt is generated, the count value in the Timer High and Low
Byte registers is reset to 0001h, and counting resumes. If no capture event occurs, upon
PS024604-1005
P R E L I M I N A R Y
Timer Operating Modes
ZILOG [ ZILOG, INC. ]
