Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
56
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 37) contains the master enable bit for all
interrupts.
Table 37. Interrupt Control Register (IRQCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQE
Reserved
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved
These bits must be 0.
PS017610-0404
Interrupt Controller
ZILOG [ ZILOG, INC. ]
