Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
222
RRC 191
SBC 188
SCF 188, 189
block diagram 95
control register definitions 98
jitter 98
SRA 191
operation 96
SRL 191
receiving data 97
SRP 189
STOP 189
transmitting data 96
IRET 190
SUB 188
SUBX 188
SWAP 191
TCM 188
IRQ0 enable high and low bit registers 51
IRQ1 enable high and low bit registers 52
IRQ2 enable high and low bit registers 53
IRR 184
TCMX 188
Irr 184
TM 188
TMX 188
TRAP 190
watch-dog timer refresh 189
XOR 190
J
jitter 98
JP 190
XORX 190
jump, conditional, relative, and relative conditional
190
instructions, eZ8 classes of 187
interrupt control register 56
interrupt controller 5, 44
architecture 44
interrupt assertion types 47
interrupt vectors and priority 47
operation 46
L
LD 189
LDC 189
LDCI 188, 189
register definitions 48
interrupt edge select register 54
interrupt port select register 55
interrupt request 0 register 48
interrupt request 1 register 49
interrupt request 2 register 50
interrupt return 190
interrupt vector listing 44
interrupts
LDE 189
LDEI 188, 189
LDX 189
LEA 189
load 189
load constant 188
load constant to/from program memory 189
load constant with auto-increment addresses 189
load effective address 189
load external data 189
load external data to/from data memory and auto-
increment addresses 188
load external to/from data memory and auto-incre-
ment addresses 189
load instructions 189
load using extended addressing 189
logical AND 190
logical AND/extended addressing 190
logical exclusive OR 190
not acknowledge 112
receive 112
SPI 105
transmit 112
UART 85
introduction 1
IR 184
Ir 184
IrDA
architecture 95
PS017610-0404
P r e l i m i n a r y
Index
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