Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
153
VDD
RS-232
Transceiver
10K Ohm
Open-Drain
Buffer
RS-232 TX
RS-232 RX
DBG Pin
Figure 88. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
Debug Mode
The operating characteristics of the Z8F640x family devices in Debug mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
•
•
•
•
The system clock operates unless in Stop mode.
All enabled on-chip peripherals operate unless in Stop mode.
Automatically exits Halt mode.
Constantly refreshes the Watch-Dog Timer, if enabled.
Entering Debug Mode
The Z8F640x family device enters Debug mode following any of the following opera-
tions:
•
•
•
•
Writing the DBGMODEbit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
Break upon a Watchpoint match.
If the DBG pin is Low when the Z8F640x family device exits Reset, the On-Chip
Debugger automatically puts the device into Debug mode.
Exiting Debug Mode
The device exits Debug mode following any of the following operations:
•
Clearing the DBGMODEbit in the OCD Control Register to 0.
PS017610-0404
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
