Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
xiv
List of Figures
Figure 1. Z8 Encore!® Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8Fxx01 in 40-Pin Dual Inline Package (DIP) . . . . . . . . . . 7
Figure 3. Z8Fxx01 in 44-Pin Plastic Leaded Chip Carrier (PLCC) . . 8
Figure 4. Z8Fxx01 in 44-Pin Low-Profile Quad Flat Package (LQFP) 9
Figure 5. Z8Fxx02 in 64-Pin Low-Profile Quad Flat Package (LQFP) 10
Figure 6. Z8Fxx02 in 68-Pin Plastic Leaded Chip Carrier (PLCC) . 11
Figure 7. Z8Fxx03 in 80-Pin Quad Flat Package (QFP) . . . . . . . . . . 12
Figure 8. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . 28
Figure 10. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . 46
Figure 12. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 13. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 14. UART Asynchronous Data Format without Parity . . . . . . 80
Figure 15. UART Asynchronous Data Format with Parity . . . . . . . . . 80
Figure 16. UART Asynchronous Multiprocessor (9-bit) Mode
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 17. Infrared Data Communication System Block Diagram . . . 95
Figure 18. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 19. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 20. SPI Configured as a Master in a Single Master,
Single Slave System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 21. SPI Configured as a Master in a Single Master,
Multiple Slave System . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 22. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 23. SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . 103
Figure 24. SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . 104
Figure 25. 7-Bit Addressed Slave Data Transfer Format . . . . . . . . . 113
Figure 26. 10-Bit Addressed Slave Data Transfer Format . . . . . . . . 114
Figure 27. Receive Data Transfer Format for a 7-Bit
Addressed Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 28. Receive Data Format for a 10-Bit Addressed Slave . . . . 116
Figure 29. Analog-to-Digital Converter Block Diagram . . . . . . . . . 133
Figure 30. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . 139
PS017610-0404
List of Figures
ZILOG [ ZILOG, INC. ]
