Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
73
information on approximate time-out delays for the minimum and maximum WDT reload
values.
Table 45. Watch-Dog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
WDT Reload Value
WDT Reload Value
(with 50kHz typical WDT oscillator frequency)
(Hex)
000004
FFFFFF
(Decimal)
4
Typical
80µs
Description
Minimum time-out delay
Maximum time-out delay
16,777,215
335.5s
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 000000Hunless a
WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes
the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog
Timer Reload registers. Counting resumes following the reload operation.\
When the Z8F640x family device is operating in Debug Mode (via the On-Chip Debug-
ger), the Watch-Dog Timer is continuously refreshed to prevent spurious Watch-Dog
Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the
Watch-Dog Timer generates either an interrupt or a Short Reset. The WDT_RESOption Bit
determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chap-
ter for information regarding programming of the WDT_RESOption Bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues
an interrupt request to the interrupt controller and sets the WDTstatus bit in the Watch-Dog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watch-Dog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watch-Dog Timer counter
rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog
Timer counter is not automatically returned to its Reload Value.
WDT Interrupt in Stop Mode
If configured to generate an interrupt when a time-out occurs and the Z8F640x family
device is in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode
Recovery and generates an interrupt request. Both the WDTstatus bit and the STOPbit in
the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP
PS017610-0404
Watch-Dog Timer
ZILOG [ ZILOG, INC. ]
