Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
111
I2C Controller
Overview
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TM
The I C Controller makes the Z8F640x family device bus-compatible with the I C pro-
tocol. The I2C Controller consists of two bidirectional bus lines—a serial data signal
(SDA) and a serial clock signal (SCL). Features of the I2C Controller include:
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Transmit and Receive Operation in Master mode
Maximum data rate of 400kbit/sec
7- and 10-bit Addressing Modes for Slaves
Unrestricted Number of Data Bytes Transmitted per Transfer
The I2C Controller in the Z8F640x family device does not operate in Slave mode.
Operation
The I2C Controller operates in Master mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
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Master transmits to a 7-bit slave
Master transmits to a 10-bit slave
Master receives from a 7-bit slave
Master receives from a 10-bit slave
SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant
bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I2C) is responsible for driving the SCL clock signal, although the clock signal
can become skewed by a slow slave device. During the high period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. When the slave has released the line,
the I2C Controller continues the transaction. All data is transferred in bytes and there is no
PS017609-0803
I2C Controller
ZILOG [ ZILOG, INC. ]
